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------------------------------------------------------------------------------
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-- This file is a part of the LPP VHDL IP LIBRARY
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-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-------------------------------------------------------------------------------
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-- Author : Jean-christophe Pellion
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-- Mail : jean-christophe.pellion@lpp.polytechnique.fr
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-- jean-christophe.pellion@easii-ic.com
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-------------------------------------------------------------------------------
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-- 1.0 - initial version
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-------------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE ieee.numeric_std.ALL;
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ENTITY lpp_waveform_dma_genvalid IS
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PORT (
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HCLK : IN STD_LOGIC;
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HRESETn : IN STD_LOGIC;
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run : IN STD_LOGIC;
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valid_in : IN STD_LOGIC;
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time_in : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
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ack_in : IN STD_LOGIC;
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valid_out : OUT STD_LOGIC;
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time_out : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
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error : OUT STD_LOGIC
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);
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END;
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ARCHITECTURE Behavioral OF lpp_waveform_dma_genvalid IS
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TYPE state_fsm IS (IDLE, VALID);
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SIGNAL state : state_fsm;
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BEGIN
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FSM_SELECT_ADDRESS : PROCESS (HCLK, HRESETn)
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BEGIN
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IF HRESETn = '0' THEN
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state <= IDLE;
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valid_out <= '0';
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error <= '0';
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time_out <= (OTHERS => '0');
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ELSIF HCLK'EVENT AND HCLK = '1' THEN
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IF run = '1' THEN
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CASE state IS
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WHEN IDLE =>
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valid_out <= valid_in;
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error <= '0';
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time_out <= time_in;
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IF valid_in = '1' THEN
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state <= VALID;
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END IF;
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WHEN VALID =>
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IF valid_in = '1' THEN
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IF ack_in = '1' THEN
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state <= VALID;
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valid_out <= '1';
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time_out <= time_in;
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ELSE
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state <= IDLE;
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error <= '1';
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valid_out <= '0';
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END IF;
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ELSIF ack_in = '1' THEN
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state <= IDLE;
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valid_out <= '0';
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END IF;
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WHEN OTHERS => NULL;
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END CASE;
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ELSE
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state <= IDLE;
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valid_out <= '0';
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error <= '0';
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time_out <= (OTHERS => '0');
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END IF;
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END IF;
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END PROCESS FSM_SELECT_ADDRESS;
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END Behavioral;
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