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------------------------------------------------------------------------------
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-- This file is a part of the LPP VHDL IP LIBRARY
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-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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------------------------------------------------------------------------------
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-- Author : Martin Morlot
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-- Mail : martin.morlot@lpp.polytechnique.fr
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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library grlib;
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use grlib.amba.all;
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use std.textio.all;
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library gaisler;
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use gaisler.libdcom.all;
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library lpp;
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use lpp.lpp_amba.all;
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--! Package contenant tous les programmes qui forment le composant int�gr� dans le l�on
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package lpp_usb is
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component ahb_ftdi_fifo is
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generic (
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oepol : integer := 0;
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hindex : integer := 0
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);
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port (
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clk : in std_logic;
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rstn : in std_logic;
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ahbi : in ahb_mst_in_type;
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ahbo : out ahb_mst_out_type;
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FTDI_RXF : in std_logic;
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FTDI_TXE : in std_logic;
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FTDI_SIWUA : out std_logic;
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FTDI_WR : out std_logic;
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FTDI_RD : out std_logic;
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FTDI_D_in : in std_logic_vector(7 downto 0);
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FTDI_D_out : out std_logic_vector(7 downto 0);
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FTDI_D_drive : out std_logic
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);
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end component;
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component ftdi_async_fifo is
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generic (
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oepol : integer := 0
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);
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port (
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clk : in std_logic;
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rstn : in std_logic;
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dcom_in : in dcom_uart_in_type;
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dcom_out : out dcom_uart_out_type;
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FTDI_RXF : in std_logic;
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FTDI_TXE : in std_logic;
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FTDI_SIWUA : out std_logic;
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FTDI_WR : out std_logic;
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FTDI_RD : out std_logic;
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FTDI_D_in : in std_logic_vector(7 downto 0);
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FTDI_D_out : out std_logic_vector(7 downto 0);
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FTDI_D_drive : out std_logic
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);
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end component;
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component ftdi_async_fifo_loopback is
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generic (
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oepol : integer := 0
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);
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port (
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clk : in std_logic;
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rstn : in std_logic;
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FTDI_RXF : in std_logic;
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FTDI_TXE : in std_logic;
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FTDI_SIWUA : out std_logic;
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FTDI_WR : out std_logic;
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FTDI_RD : out std_logic;
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FTDI_D_in : in std_logic_vector(7 downto 0);
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FTDI_D_out : out std_logic_vector(7 downto 0);
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FTDI_D_drive : out std_logic
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);
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end component;
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component FX2_Driver is
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port(
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clk : in STD_LOGIC;
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if_clk : out STD_LOGIC;
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reset : in std_logic;
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flagb : in STD_LOGIC;
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slwr : out STD_LOGIC;
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slrd : out std_logic;
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pktend : out STD_LOGIC;
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sloe : out STD_LOGIC;
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fdbusw : out std_logic_vector (7 downto 0);
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fifoadr : out std_logic_vector (1 downto 0);
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FULL : out std_logic;
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Write : in std_logic;
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Data : in std_logic_vector(7 downto 0)
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);
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end component;
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component FX2_WithFIFO is
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generic(
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tech : integer := 0;
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Mem_use : integer := 0;
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Enable_ReUse : std_logic := '0';
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fifoCount : integer range 2 to 100 := 8;
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abits : integer range 2 to 12 := 8
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);
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port(
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clk : in STD_LOGIC;
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if_clk : out STD_LOGIC;
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reset : in std_logic;
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flagb : in STD_LOGIC;
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slwr : out STD_LOGIC;
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slrd : out std_logic;
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pktend : out STD_LOGIC;
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sloe : out STD_LOGIC;
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fdbusw : out std_logic_vector (7 downto 0);
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fifoadr : out std_logic_vector (1 downto 0);
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FULL : out std_logic;
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Write : in std_logic;
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Data : in std_logic_vector(7 downto 0)
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);
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end component;
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component APB_USB is
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generic (
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pindex : integer := 0;
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paddr : integer := 0;
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pmask : integer := 16#fff#;
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pirq : integer := 0;
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abits : integer := 8;
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DataMax : integer := 1024);
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port (
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clk : in std_logic; --! Horloge du composant
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rst : in std_logic; --! Reset general du composant
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flagC : in std_logic;
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flagB : in std_logic;
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ifclk : out std_logic;
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sloe : out std_logic;
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slrd : out std_logic;
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slwr : out std_logic;
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pktend : out std_logic;
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fifoadr : out std_logic_vector(1 downto 0);
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fdbusrw : inout std_logic_vector(7 downto 0);
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apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus
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apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
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);
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end component;
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component RWbuf is
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generic(DataMax : integer := 1024);
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port(
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clk : in std_logic;
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rst : in std_logic;
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flagC : in std_logic;
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flagB : in std_logic;
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IOselect : in std_logic;
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ifclk : out std_logic;
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sloe : out std_logic;
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slrd : out std_logic;
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slwr : out std_logic;
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pktend : out std_logic;
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fifoadr : out std_logic_vector(1 downto 0);
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fdbusrw : inout std_logic_vector(7 downto 0)
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);
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end component;
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end package;
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