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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE ieee.numeric_std.ALL;
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LIBRARY lpp;
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USE lpp.lpp_ad_conv.ALL;
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USE lpp.iir_filter.ALL;
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USE lpp.FILTERcfg.ALL;
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USE lpp.lpp_memory.ALL;
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USE lpp.lpp_waveform_pkg.ALL;
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USE lpp.general_purpose.SYNC_FF;
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LIBRARY techmap;
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USE techmap.gencomp.ALL;
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LIBRARY grlib;
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USE grlib.amba.ALL;
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USE grlib.stdlib.ALL;
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USE grlib.devices.ALL;
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USE GRLIB.DMA2AHB_Package.ALL;
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ENTITY lpp_top_lfr_wf_picker_ip IS
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GENERIC(
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hindex : INTEGER := 2;
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nb_burst_available_size : INTEGER := 11;
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nb_snapshot_param_size : INTEGER := 11;
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delta_snapshot_size : INTEGER := 16;
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delta_f2_f0_size : INTEGER := 10;
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delta_f2_f1_size : INTEGER := 10;
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tech : INTEGER := 0;
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Mem_use : INTEGER := use_RAM
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);
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PORT (
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sample : IN Samples(7 DOWNTO 0);
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sample_val : IN STD_LOGIC;
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--
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clk : IN STD_LOGIC;
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rstn : IN STD_LOGIC;
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--
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sample_f0_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
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sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
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--
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sample_f1_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
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sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
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--
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sample_f2_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
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sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
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--
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sample_f3_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
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sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
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-- AMBA AHB Master Interface
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AHB_Master_In : IN AHB_Mst_In_Type;
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AHB_Master_Out : OUT AHB_Mst_Out_Type;
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coarse_time_0 : IN STD_LOGIC;
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--config
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data_shaping_SP0 : IN STD_LOGIC;
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data_shaping_SP1 : IN STD_LOGIC;
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data_shaping_R0 : IN STD_LOGIC;
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data_shaping_R1 : IN STD_LOGIC;
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delta_snapshot : IN STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0);
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delta_f2_f1 : IN STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0);
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delta_f2_f0 : IN STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0);
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enable_f0 : IN STD_LOGIC;
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enable_f1 : IN STD_LOGIC;
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enable_f2 : IN STD_LOGIC;
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enable_f3 : IN STD_LOGIC;
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burst_f0 : IN STD_LOGIC;
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burst_f1 : IN STD_LOGIC;
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burst_f2 : IN STD_LOGIC;
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nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
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nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
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status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
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status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
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status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
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status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- New data f(i) before the current data is write by dma
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addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
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);
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END lpp_top_lfr_wf_picker_ip;
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ARCHITECTURE tb OF lpp_top_lfr_wf_picker_ip IS
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COMPONENT Downsampling
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GENERIC (
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ChanelCount : INTEGER;
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SampleSize : INTEGER;
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DivideParam : INTEGER);
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PORT (
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clk : IN STD_LOGIC;
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rstn : IN STD_LOGIC;
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sample_in_val : IN STD_LOGIC;
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sample_in : IN samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0);
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sample_out_val : OUT STD_LOGIC;
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sample_out : OUT samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0));
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END COMPONENT;
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COMPONENT SYNC_FF
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GENERIC (
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NB_FF_OF_SYNC : INTEGER);
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PORT (
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clk : IN STD_LOGIC;
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rstn : IN STD_LOGIC;
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A : IN STD_LOGIC;
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A_sync : OUT STD_LOGIC);
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END COMPONENT;
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-----------------------------------------------------------------------------
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CONSTANT ChanelCount : INTEGER := 8;
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-----------------------------------------------------------------------------
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SIGNAL sample_val_delay : STD_LOGIC;
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-----------------------------------------------------------------------------
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CONSTANT Coef_SZ : INTEGER := 9;
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CONSTANT CoefCntPerCel : INTEGER := 6;
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CONSTANT CoefPerCel : INTEGER := 5;
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CONSTANT Cels_count : INTEGER := 5;
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SIGNAL coefs : STD_LOGIC_VECTOR((Coef_SZ*CoefCntPerCel*Cels_count)-1 DOWNTO 0);
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SIGNAL coefs_v2 : STD_LOGIC_VECTOR((Coef_SZ*CoefPerCel*Cels_count)-1 DOWNTO 0);
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SIGNAL sample_filter_in : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
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SIGNAL sample_filter_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
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--
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SIGNAL sample_filter_v2_out_val : STD_LOGIC;
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SIGNAL sample_filter_v2_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
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-----------------------------------------------------------------------------
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--SIGNAL sample_filter_v2_out_reg : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
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--SIGNAL sample_filter_v2_out_reg_val : STD_LOGIC;
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--SIGNAL sample_filter_v2_out_reg_val_s : STD_LOGIC;
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--SIGNAL sample_filter_v2_out_reg_val_s2 : STD_LOGIC;
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--SIGNAL only_one_hot : STD_LOGIC;
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--SIGNAL sample_filter_v2_out_sync_val_t : STD_LOGIC;
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--SIGNAL sample_filter_v2_out_sync_val : STD_LOGIC;
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--SIGNAL sample_filter_v2_out_sync : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
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-----------------------------------------------------------------------------
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SIGNAL sample_data_shaping_out_val : STD_LOGIC;
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SIGNAL sample_data_shaping_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
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SIGNAL sample_data_shaping_f0_s : STD_LOGIC_VECTOR(17 DOWNTO 0);
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SIGNAL sample_data_shaping_f1_s : STD_LOGIC_VECTOR(17 DOWNTO 0);
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SIGNAL sample_data_shaping_f2_s : STD_LOGIC_VECTOR(17 DOWNTO 0);
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SIGNAL sample_data_shaping_f1_f0_s : STD_LOGIC_VECTOR(17 DOWNTO 0);
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SIGNAL sample_data_shaping_f2_f1_s : STD_LOGIC_VECTOR(17 DOWNTO 0);
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-----------------------------------------------------------------------------
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SIGNAL sample_filter_v2_out_val_s : STD_LOGIC;
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SIGNAL sample_filter_v2_out_s : samplT(ChanelCount-1 DOWNTO 0, 15 DOWNTO 0);
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-----------------------------------------------------------------------------
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SIGNAL sample_f0_val : STD_LOGIC;
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SIGNAL sample_f0 : samplT(ChanelCount-1 DOWNTO 0, 15 DOWNTO 0);
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SIGNAL sample_f0_s : samplT(5 DOWNTO 0, 15 DOWNTO 0);
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--
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SIGNAL sample_f1_val : STD_LOGIC;
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SIGNAL sample_f1 : samplT(ChanelCount-1 DOWNTO 0, 15 DOWNTO 0);
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SIGNAL sample_f1_s : samplT(5 DOWNTO 0, 15 DOWNTO 0);
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--
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SIGNAL sample_f2_val : STD_LOGIC;
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SIGNAL sample_f2 : samplT(5 DOWNTO 0, 15 DOWNTO 0);
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--
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SIGNAL sample_f3_val : STD_LOGIC;
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SIGNAL sample_f3 : samplT(5 DOWNTO 0, 15 DOWNTO 0);
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-----------------------------------------------------------------------------
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SIGNAL data_f0_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0');
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SIGNAL data_f1_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0');
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SIGNAL data_f2_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0');
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SIGNAL data_f3_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0');
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-----------------------------------------------------------------------------
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SIGNAL sample_f0_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
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SIGNAL sample_f1_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
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SIGNAL sample_f2_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
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SIGNAL sample_f3_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
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BEGIN
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-----------------------------------------------------------------------------
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PROCESS (clk, rstn)
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BEGIN -- PROCESS
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IF rstn = '0' THEN -- asynchronous reset (active low)
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sample_val_delay <= '0';
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ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
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sample_val_delay <= sample_val;
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END IF;
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END PROCESS;
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-----------------------------------------------------------------------------
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ChanelLoop : FOR i IN 0 TO ChanelCount-1 GENERATE
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SampleLoop : FOR j IN 0 TO 15 GENERATE
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sample_filter_in(i, j) <= sample(i)(j);
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END GENERATE;
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sample_filter_in(i, 16) <= sample(i)(15);
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sample_filter_in(i, 17) <= sample(i)(15);
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END GENERATE;
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coefs_v2 <= CoefsInitValCst_v2;
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IIR_CEL_CTRLR_v2_1 : IIR_CEL_CTRLR_v2
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GENERIC MAP (
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tech => 0,
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Mem_use => Mem_use, -- use_RAM
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Sample_SZ => 18,
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Coef_SZ => Coef_SZ,
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Coef_Nb => 25,
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Coef_sel_SZ => 5,
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Cels_count => Cels_count,
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ChanelsCount => ChanelCount)
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PORT MAP (
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rstn => rstn,
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clk => clk,
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virg_pos => 7,
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coefs => coefs_v2,
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sample_in_val => sample_val_delay,
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sample_in => sample_filter_in,
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sample_out_val => sample_filter_v2_out_val,
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sample_out => sample_filter_v2_out);
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-----------------------------------------------------------------------------
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-- RESYNC STAGE
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-----------------------------------------------------------------------------
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--all_sample_reg : FOR I IN ChanelCount-1 DOWNTO 0 GENERATE
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-- all_data_reg : FOR J IN 17 DOWNTO 0 GENERATE
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-- PROCESS (cnv_clk, cnv_rstn)
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-- BEGIN -- PROCESS
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-- IF cnv_rstn = '0' THEN -- asynchronous reset (active low)
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-- sample_filter_v2_out_reg(I, J) <= '0';
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-- ELSIF cnv_clk'EVENT AND cnv_clk = '1' THEN -- rising clock edge
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-- IF sample_filter_v2_out_val = '1' THEN
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-- sample_filter_v2_out_reg(I, J) <= sample_filter_v2_out(I, J);
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-- END IF;
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-- END IF;
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-- END PROCESS;
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-- END GENERATE all_data_reg;
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--END GENERATE all_sample_reg;
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--PROCESS (cnv_clk, cnv_rstn)
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--BEGIN -- PROCESS
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-- IF cnv_rstn = '0' THEN -- asynchronous reset (active low)
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-- sample_filter_v2_out_reg_val <= '0';
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-- ELSIF cnv_clk'EVENT AND cnv_clk = '1' THEN -- rising clock edge
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-- IF sample_filter_v2_out_val = '1' THEN
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-- sample_filter_v2_out_reg_val <= '1';
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-- ELSIF sample_filter_v2_out_reg_val_s2 = '1' THEN
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-- sample_filter_v2_out_reg_val <= '0';
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-- END IF;
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-- END IF;
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--END PROCESS;
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--SYNC_FF_1 : SYNC_FF
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-- GENERIC MAP (
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-- NB_FF_OF_SYNC => 2)
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-- PORT MAP (
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-- clk => clk,
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-- rstn => rstn,
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-- A => sample_filter_v2_out_reg_val,
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-- A_sync => sample_filter_v2_out_reg_val_s);
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--SYNC_FF_2 : SYNC_FF
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-- GENERIC MAP (
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-- NB_FF_OF_SYNC => 2)
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-- PORT MAP (
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-- clk => cnv_clk,
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-- rstn => cnv_rstn,
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-- A => sample_filter_v2_out_reg_val_s,
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-- A_sync => sample_filter_v2_out_reg_val_s2);
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--PROCESS (clk, rstn)
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--BEGIN -- PROCESS
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-- IF rstn = '0' THEN -- asynchronous reset (active low)
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-- sample_filter_v2_out_sync_val_t <= '0';
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-- sample_filter_v2_out_sync_val <= '0';
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-- only_one_hot <= '0';
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-- ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
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-- sample_filter_v2_out_sync_val_t <= sample_filter_v2_out_reg_val_s AND NOT only_one_hot;
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-- only_one_hot <= sample_filter_v2_out_reg_val_s;
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-- sample_filter_v2_out_sync_val <= sample_filter_v2_out_sync_val_t;
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-- END IF;
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--END PROCESS;
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--all_sample_reg2 : FOR I IN ChanelCount-1 DOWNTO 0 GENERATE
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-- all_data_reg : FOR J IN 17 DOWNTO 0 GENERATE
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-- PROCESS (clk, cnv_rstn)
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-- BEGIN -- PROCESS
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-- IF cnv_rstn = '0' THEN -- asynchronous reset (active low)
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-- sample_filter_v2_out_sync(I,J) <= '0';
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-- ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
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-- IF sample_filter_v2_out_sync_val_t = '1' THEN
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-- sample_filter_v2_out_sync(I,J) <= sample_filter_v2_out_reg(I,J);
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-- END IF;
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-- END IF;
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-- END PROCESS;
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-- END GENERATE all_data_reg;
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--END GENERATE all_sample_reg2;
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-----------------------------------------------------------------------------
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-- DATA_SHAPING
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-----------------------------------------------------------------------------
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all_data_shaping_in_loop : FOR I IN 17 DOWNTO 0 GENERATE
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sample_data_shaping_f0_s(I) <= sample_filter_v2_out(0, I);
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sample_data_shaping_f1_s(I) <= sample_filter_v2_out(1, I);
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sample_data_shaping_f2_s(I) <= sample_filter_v2_out(2, I);
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END GENERATE all_data_shaping_in_loop;
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sample_data_shaping_f1_f0_s <= sample_data_shaping_f1_s - sample_data_shaping_f0_s;
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sample_data_shaping_f2_f1_s <= sample_data_shaping_f2_s - sample_data_shaping_f1_s;
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PROCESS (clk, rstn)
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BEGIN -- PROCESS
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IF rstn = '0' THEN -- asynchronous reset (active low)
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sample_data_shaping_out_val <= '0';
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ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
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sample_data_shaping_out_val <= sample_filter_v2_out_val;
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END IF;
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END PROCESS;
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SampleLoop_data_shaping : FOR j IN 0 TO 17 GENERATE
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PROCESS (clk, rstn)
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BEGIN
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IF rstn = '0' THEN
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sample_data_shaping_out(0, j) <= '0';
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sample_data_shaping_out(1, j) <= '0';
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sample_data_shaping_out(2, j) <= '0';
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sample_data_shaping_out(3, j) <= '0';
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sample_data_shaping_out(4, j) <= '0';
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sample_data_shaping_out(5, j) <= '0';
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sample_data_shaping_out(6, j) <= '0';
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sample_data_shaping_out(7, j) <= '0';
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ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
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sample_data_shaping_out(0, j) <= sample_filter_v2_out(0, j);
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IF data_shaping_SP0 = '1' THEN
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sample_data_shaping_out(1, j) <= sample_data_shaping_f1_f0_s(j);
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ELSE
|
|
|
sample_data_shaping_out(1, j) <= sample_filter_v2_out(1, j);
|
|
|
END IF;
|
|
|
IF data_shaping_SP1 = '1' THEN
|
|
|
sample_data_shaping_out(2, j) <= sample_data_shaping_f2_f1_s(j);
|
|
|
ELSE
|
|
|
sample_data_shaping_out(2, j) <= sample_filter_v2_out(2, j);
|
|
|
END IF;
|
|
|
sample_data_shaping_out(3, j) <= sample_filter_v2_out(3, j);
|
|
|
sample_data_shaping_out(4, j) <= sample_filter_v2_out(4, j);
|
|
|
sample_data_shaping_out(5, j) <= sample_filter_v2_out(5, j);
|
|
|
sample_data_shaping_out(6, j) <= sample_filter_v2_out(6, j);
|
|
|
sample_data_shaping_out(7, j) <= sample_filter_v2_out(7, j);
|
|
|
END IF;
|
|
|
END PROCESS;
|
|
|
END GENERATE;
|
|
|
|
|
|
sample_filter_v2_out_val_s <= sample_data_shaping_out_val;
|
|
|
ChanelLoopOut : FOR i IN 0 TO 7 GENERATE
|
|
|
SampleLoopOut : FOR j IN 0 TO 15 GENERATE
|
|
|
sample_filter_v2_out_s(i, j) <= sample_data_shaping_out(i, j);
|
|
|
END GENERATE;
|
|
|
END GENERATE;
|
|
|
-----------------------------------------------------------------------------
|
|
|
-- F0 -- @24.576 kHz
|
|
|
-----------------------------------------------------------------------------
|
|
|
Downsampling_f0 : Downsampling
|
|
|
GENERIC MAP (
|
|
|
ChanelCount => 8,
|
|
|
SampleSize => 16,
|
|
|
DivideParam => 4)
|
|
|
PORT MAP (
|
|
|
clk => clk,
|
|
|
rstn => rstn,
|
|
|
sample_in_val => sample_filter_v2_out_val_s,
|
|
|
sample_in => sample_filter_v2_out_s,
|
|
|
sample_out_val => sample_f0_val,
|
|
|
sample_out => sample_f0);
|
|
|
|
|
|
all_bit_sample_f0 : FOR I IN 15 DOWNTO 0 GENERATE
|
|
|
sample_f0_wdata_s(I) <= sample_f0(0, I); -- V
|
|
|
sample_f0_wdata_s(16*1+I) <= sample_f0(1, I) WHEN data_shaping_R0 = '1' ELSE sample_f0(3, I); -- E1
|
|
|
sample_f0_wdata_s(16*2+I) <= sample_f0(2, I) WHEN data_shaping_R0 = '1' ELSE sample_f0(4, I); -- E2
|
|
|
sample_f0_wdata_s(16*3+I) <= sample_f0(5, I); -- B1
|
|
|
sample_f0_wdata_s(16*4+I) <= sample_f0(6, I); -- B2
|
|
|
sample_f0_wdata_s(16*5+I) <= sample_f0(7, I); -- B3
|
|
|
END GENERATE all_bit_sample_f0;
|
|
|
|
|
|
sample_f0_wen <= NOT(sample_f0_val) &
|
|
|
NOT(sample_f0_val) &
|
|
|
NOT(sample_f0_val) &
|
|
|
NOT(sample_f0_val) &
|
|
|
NOT(sample_f0_val) &
|
|
|
NOT(sample_f0_val);
|
|
|
|
|
|
-----------------------------------------------------------------------------
|
|
|
-- F1 -- @4096 Hz
|
|
|
-----------------------------------------------------------------------------
|
|
|
Downsampling_f1 : Downsampling
|
|
|
GENERIC MAP (
|
|
|
ChanelCount => 8,
|
|
|
SampleSize => 16,
|
|
|
DivideParam => 6)
|
|
|
PORT MAP (
|
|
|
clk => clk,
|
|
|
rstn => rstn,
|
|
|
sample_in_val => sample_f0_val ,
|
|
|
sample_in => sample_f0,
|
|
|
sample_out_val => sample_f1_val,
|
|
|
sample_out => sample_f1);
|
|
|
|
|
|
all_bit_sample_f1 : FOR I IN 15 DOWNTO 0 GENERATE
|
|
|
sample_f1_wdata_s(I) <= sample_f1(0, I); -- V
|
|
|
sample_f1_wdata_s(16*1+I) <= sample_f1(1, I) WHEN data_shaping_R1 = '1' ELSE sample_f1(3, I); -- E1
|
|
|
sample_f1_wdata_s(16*2+I) <= sample_f1(2, I) WHEN data_shaping_R1 = '1' ELSE sample_f1(4, I); -- E2
|
|
|
sample_f1_wdata_s(16*3+I) <= sample_f1(5, I); -- B1
|
|
|
sample_f1_wdata_s(16*4+I) <= sample_f1(6, I); -- B2
|
|
|
sample_f1_wdata_s(16*5+I) <= sample_f1(7, I); -- B3
|
|
|
END GENERATE all_bit_sample_f1;
|
|
|
|
|
|
sample_f1_wen <= NOT(sample_f1_val) &
|
|
|
NOT(sample_f1_val) &
|
|
|
NOT(sample_f1_val) &
|
|
|
NOT(sample_f1_val) &
|
|
|
NOT(sample_f1_val) &
|
|
|
NOT(sample_f1_val);
|
|
|
|
|
|
-----------------------------------------------------------------------------
|
|
|
-- F2 -- @256 Hz
|
|
|
-----------------------------------------------------------------------------
|
|
|
all_bit_sample_f0_s : FOR I IN 15 DOWNTO 0 GENERATE
|
|
|
sample_f0_s(0, I) <= sample_f0(0, I); -- V
|
|
|
sample_f0_s(1, I) <= sample_f0(1, I); -- E1
|
|
|
sample_f0_s(2, I) <= sample_f0(2, I); -- E2
|
|
|
sample_f0_s(3, I) <= sample_f0(5, I); -- B1
|
|
|
sample_f0_s(4, I) <= sample_f0(6, I); -- B2
|
|
|
sample_f0_s(5, I) <= sample_f0(7, I); -- B3
|
|
|
END GENERATE all_bit_sample_f0_s;
|
|
|
|
|
|
Downsampling_f2 : Downsampling
|
|
|
GENERIC MAP (
|
|
|
ChanelCount => 6,
|
|
|
SampleSize => 16,
|
|
|
DivideParam => 96)
|
|
|
PORT MAP (
|
|
|
clk => clk,
|
|
|
rstn => rstn,
|
|
|
sample_in_val => sample_f0_val ,
|
|
|
sample_in => sample_f0_s,
|
|
|
sample_out_val => sample_f2_val,
|
|
|
sample_out => sample_f2);
|
|
|
|
|
|
sample_f2_wen <= NOT(sample_f2_val) &
|
|
|
NOT(sample_f2_val) &
|
|
|
NOT(sample_f2_val) &
|
|
|
NOT(sample_f2_val) &
|
|
|
NOT(sample_f2_val) &
|
|
|
NOT(sample_f2_val);
|
|
|
|
|
|
all_bit_sample_f2 : FOR I IN 15 DOWNTO 0 GENERATE
|
|
|
sample_f2_wdata_s(I) <= sample_f2(0, I);
|
|
|
sample_f2_wdata_s(16*1+I) <= sample_f2(1, I);
|
|
|
sample_f2_wdata_s(16*2+I) <= sample_f2(2, I);
|
|
|
sample_f2_wdata_s(16*3+I) <= sample_f2(3, I);
|
|
|
sample_f2_wdata_s(16*4+I) <= sample_f2(4, I);
|
|
|
sample_f2_wdata_s(16*5+I) <= sample_f2(5, I);
|
|
|
END GENERATE all_bit_sample_f2;
|
|
|
|
|
|
-----------------------------------------------------------------------------
|
|
|
-- F3 -- @16 Hz
|
|
|
-----------------------------------------------------------------------------
|
|
|
all_bit_sample_f1_s : FOR I IN 15 DOWNTO 0 GENERATE
|
|
|
sample_f1_s(0, I) <= sample_f1(0, I); -- V
|
|
|
sample_f1_s(1, I) <= sample_f1(1, I); -- E1
|
|
|
sample_f1_s(2, I) <= sample_f1(2, I); -- E2
|
|
|
sample_f1_s(3, I) <= sample_f1(5, I); -- B1
|
|
|
sample_f1_s(4, I) <= sample_f1(6, I); -- B2
|
|
|
sample_f1_s(5, I) <= sample_f1(7, I); -- B3
|
|
|
END GENERATE all_bit_sample_f1_s;
|
|
|
|
|
|
Downsampling_f3 : Downsampling
|
|
|
GENERIC MAP (
|
|
|
ChanelCount => 6,
|
|
|
SampleSize => 16,
|
|
|
DivideParam => 256)
|
|
|
PORT MAP (
|
|
|
clk => clk,
|
|
|
rstn => rstn,
|
|
|
sample_in_val => sample_f1_val ,
|
|
|
sample_in => sample_f1_s,
|
|
|
sample_out_val => sample_f3_val,
|
|
|
sample_out => sample_f3);
|
|
|
|
|
|
sample_f3_wen <= (NOT sample_f3_val) &
|
|
|
(NOT sample_f3_val) &
|
|
|
(NOT sample_f3_val) &
|
|
|
(NOT sample_f3_val) &
|
|
|
(NOT sample_f3_val) &
|
|
|
(NOT sample_f3_val);
|
|
|
|
|
|
all_bit_sample_f3 : FOR I IN 15 DOWNTO 0 GENERATE
|
|
|
sample_f3_wdata_s(I) <= sample_f3(0, I);
|
|
|
sample_f3_wdata_s(16*1+I) <= sample_f3(1, I);
|
|
|
sample_f3_wdata_s(16*2+I) <= sample_f3(2, I);
|
|
|
sample_f3_wdata_s(16*3+I) <= sample_f3(3, I);
|
|
|
sample_f3_wdata_s(16*4+I) <= sample_f3(4, I);
|
|
|
sample_f3_wdata_s(16*5+I) <= sample_f3(5, I);
|
|
|
END GENERATE all_bit_sample_f3;
|
|
|
|
|
|
lpp_waveform_1 : lpp_waveform
|
|
|
GENERIC MAP (
|
|
|
hindex => hindex,
|
|
|
tech => tech,
|
|
|
data_size => 160,
|
|
|
nb_burst_available_size => nb_burst_available_size,
|
|
|
nb_snapshot_param_size => nb_snapshot_param_size,
|
|
|
delta_snapshot_size => delta_snapshot_size,
|
|
|
delta_f2_f0_size => delta_f2_f0_size,
|
|
|
delta_f2_f1_size => delta_f2_f1_size)
|
|
|
PORT MAP (
|
|
|
clk => clk,
|
|
|
rstn => rstn,
|
|
|
|
|
|
AHB_Master_In => AHB_Master_In,
|
|
|
AHB_Master_Out => AHB_Master_Out,
|
|
|
|
|
|
coarse_time_0 => coarse_time_0, -- IN
|
|
|
delta_snapshot => delta_snapshot, -- IN
|
|
|
delta_f2_f1 => delta_f2_f1, -- IN
|
|
|
delta_f2_f0 => delta_f2_f0, -- IN
|
|
|
enable_f0 => enable_f0, -- IN
|
|
|
enable_f1 => enable_f1, -- IN
|
|
|
enable_f2 => enable_f2, -- IN
|
|
|
enable_f3 => enable_f3, -- IN
|
|
|
burst_f0 => burst_f0, -- IN
|
|
|
burst_f1 => burst_f1, -- IN
|
|
|
burst_f2 => burst_f2, -- IN
|
|
|
nb_burst_available => nb_burst_available,
|
|
|
nb_snapshot_param => nb_snapshot_param,
|
|
|
status_full => status_full,
|
|
|
status_full_ack => status_full_ack, -- IN
|
|
|
status_full_err => status_full_err,
|
|
|
status_new_err => status_new_err,
|
|
|
|
|
|
addr_data_f0 => addr_data_f0, -- IN
|
|
|
addr_data_f1 => addr_data_f1, -- IN
|
|
|
addr_data_f2 => addr_data_f2, -- IN
|
|
|
addr_data_f3 => addr_data_f3, -- IN
|
|
|
|
|
|
data_f0_in => data_f0_in_valid,
|
|
|
data_f1_in => data_f1_in_valid,
|
|
|
data_f2_in => data_f2_in_valid,
|
|
|
data_f3_in => data_f3_in_valid,
|
|
|
|
|
|
data_f0_in_valid => sample_f0_val,
|
|
|
data_f1_in_valid => sample_f1_val,
|
|
|
data_f2_in_valid => sample_f2_val,
|
|
|
data_f3_in_valid => sample_f3_val);
|
|
|
|
|
|
data_f0_in_valid((4*16)-1 DOWNTO 0) <= (OTHERS => '0');
|
|
|
data_f1_in_valid((4*16)-1 DOWNTO 0) <= (OTHERS => '0');
|
|
|
data_f2_in_valid((4*16)-1 DOWNTO 0) <= (OTHERS => '0');
|
|
|
data_f3_in_valid((4*16)-1 DOWNTO 0) <= (OTHERS => '0');
|
|
|
|
|
|
data_f0_in_valid((10*16)-1 DOWNTO (4*16)) <= sample_f0_wdata_s;
|
|
|
data_f1_in_valid((10*16)-1 DOWNTO (4*16)) <= sample_f1_wdata_s;
|
|
|
data_f2_in_valid((10*16)-1 DOWNTO (4*16)) <= sample_f2_wdata_s;
|
|
|
data_f3_in_valid((10*16)-1 DOWNTO (4*16)) <= sample_f3_wdata_s;
|
|
|
|
|
|
sample_f0_wdata <= sample_f0_wdata_s;
|
|
|
sample_f1_wdata <= sample_f1_wdata_s;
|
|
|
sample_f2_wdata <= sample_f2_wdata_s;
|
|
|
sample_f3_wdata <= sample_f3_wdata_s;
|
|
|
|
|
|
END tb;
|
|
|
|
