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------------------------------------------------------------------------------
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-- This file is a part of the LPP VHDL IP LIBRARY
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-- Copyright (C) 2011, Laboratory of Plasmas Physic - CNRS
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-------------------------------------------------------------------------------
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-- Author : Alexis Jeandet
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-- Mail : alexis.jeandet@lpp.polytechnique.fr
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-------------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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LIBRARY gaisler;
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USE gaisler.misc.ALL;
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USE gaisler.memctrl.ALL;
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LIBRARY techmap;
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USE techmap.gencomp.ALL;
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USE techmap.allclkgen.ALL;
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ENTITY ssram_plugin IS
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GENERIC (tech : INTEGER := 0);
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PORT
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(
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clk : IN STD_LOGIC;
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mem_ctrlr_o : IN memory_out_type;
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SSRAM_CLK : OUT STD_LOGIC;
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nBWa : OUT STD_LOGIC;
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nBWb : OUT STD_LOGIC;
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nBWc : OUT STD_LOGIC;
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nBWd : OUT STD_LOGIC;
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nBWE : OUT STD_LOGIC;
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nADSC : OUT STD_LOGIC;
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nADSP : OUT STD_LOGIC;
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nADV : OUT STD_LOGIC;
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nGW : OUT STD_LOGIC;
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nCE1 : OUT STD_LOGIC;
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CE2 : OUT STD_LOGIC;
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nCE3 : OUT STD_LOGIC;
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nOE : OUT STD_LOGIC;
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MODE : OUT STD_LOGIC;
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ZZ : OUT STD_LOGIC
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);
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END ENTITY;
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ARCHITECTURE ar_ssram_plugin OF ssram_plugin IS
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SIGNAL nADSPint : STD_LOGIC := '1';
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SIGNAL nOEint : STD_LOGIC := '1';
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SIGNAL RAMSN_reg : STD_LOGIC := '1';
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SIGNAL OEreg : STD_LOGIC := '1';
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SIGNAL nBWaint : STD_LOGIC := '1';
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SIGNAL nBWbint : STD_LOGIC := '1';
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SIGNAL nBWcint : STD_LOGIC := '1';
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SIGNAL nBWdint : STD_LOGIC := '1';
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SIGNAL nBWEint : STD_LOGIC := '1';
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SIGNAL nCE1int : STD_LOGIC := '1';
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SIGNAL CE2int : STD_LOGIC := '0';
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SIGNAL nCE3int : STD_LOGIC := '1';
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TYPE stateT IS (idle, st1, st2, st3, st4);
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SIGNAL state : stateT;
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--SIGNAL nclk : STD_LOGIC;
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BEGIN
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PROCESS(clk , mem_ctrlr_o.RAMSN(0))
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BEGIN
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IF mem_ctrlr_o.RAMSN(0) = '1' then
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state <= idle;
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ELSIF clk = '1' and clk'event then
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CASE state IS
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WHEN idle =>
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state <= st1;
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WHEN st1 =>
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state <= st2;
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WHEN st2 =>
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state <= st3;
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WHEN st3 =>
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state <= st4;
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WHEN st4 =>
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state <= st1;
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END CASE;
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END IF;
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END PROCESS;
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--nclk <= NOT clk;
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ssram_clk_pad : outpad GENERIC MAP (tech => tech)
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PORT MAP (SSRAM_CLK, NOT clk);
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nBWaint <= mem_ctrlr_o.WRN(3)OR mem_ctrlr_o.ramsn(0);
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nBWa_pad : outpad GENERIC MAP (tech => tech)
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PORT MAP (nBWa, nBWaint);
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nBWbint <= mem_ctrlr_o.WRN(2)OR mem_ctrlr_o.ramsn(0);
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nBWb_pad : outpad GENERIC MAP (tech => tech)
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PORT MAP (nBWb, nBWbint);
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nBWcint <= mem_ctrlr_o.WRN(1)OR mem_ctrlr_o.ramsn(0);
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nBWc_pad : outpad GENERIC MAP (tech => tech)
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PORT MAP (nBWc, nBWcint);
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nBWdint <= mem_ctrlr_o.WRN(0)OR mem_ctrlr_o.ramsn(0);
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nBWd_pad : outpad GENERIC MAP (tech => tech)
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PORT MAP (nBWd, nBWdint);
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nBWEint <= mem_ctrlr_o.WRITEN OR mem_ctrlr_o.ramsn(0);
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nBWE_pad : outpad GENERIC MAP (tech => tech)
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PORT MAP (nBWE, nBWEint);
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nADSC_pad : outpad GENERIC MAP (tech => tech)
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PORT MAP (nADSC, '1');
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--nADSPint <= not((RAMSN_reg xor mem_ctrlr_o.RAMSN(0)) and RAMSN_reg);
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nADSPint <= '0' WHEN state = st1 ELSE '1';
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PROCESS(clk)
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BEGIN
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IF clk'EVENT AND clk = '1' THEN
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RAMSN_reg <= mem_ctrlr_o.RAMSN(0);
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END IF;
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END PROCESS;
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nADSP_pad : outpad GENERIC MAP (tech => tech)
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PORT MAP (nADSP, nADSPint);
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nADV_pad : outpad GENERIC MAP (tech => tech)
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PORT MAP (nADV, '1');
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nGW_pad : outpad GENERIC MAP (tech => tech)
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PORT MAP (nGW, '1');
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nCE1int <= nADSPint OR mem_ctrlr_o.address(31) OR (NOT mem_ctrlr_o.address(30)) OR mem_ctrlr_o.address(29) OR mem_ctrlr_o.address(28);
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CE2int <= (NOT mem_ctrlr_o.address(27)) AND (NOT mem_ctrlr_o.address(26)) AND (NOT mem_ctrlr_o.address(25)) AND (NOT mem_ctrlr_o.address(24));
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nCE3int <= mem_ctrlr_o.address(23) OR mem_ctrlr_o.address(22) OR mem_ctrlr_o.address(21) OR mem_ctrlr_o.address(20);
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nCE1_pad : outpad GENERIC MAP (tech => tech)
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PORT MAP (nCE1, nCE1int);
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CE2_pad : outpad GENERIC MAP (tech => tech)
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PORT MAP (CE2, CE2int);
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nCE3_pad : outpad GENERIC MAP (tech => tech)
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PORT MAP (nCE3, nCE3int);
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nOE_pad : outpad GENERIC MAP (tech => tech)
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PORT MAP (nOE, nOEint);
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PROCESS(clk)
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BEGIN
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IF clk'EVENT AND clk = '1' THEN
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OEreg <= mem_ctrlr_o.OEN;
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END IF;
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END PROCESS;
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--nOEint <= OEreg or mem_ctrlr_o.RAMOEN(0);
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nOEint <= '0' WHEN state = st2 OR state = st3 OR state = st4 ELSE '1';
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MODE_pad : outpad GENERIC MAP (tech => tech)
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PORT MAP (MODE, '0');
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ZZ_pad : outpad GENERIC MAP (tech => tech)
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PORT MAP (ZZ, '0');
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END ARCHITECTURE;
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