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------------------------------------------------------------------------------
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-- This file is a part of the LPP VHDL IP LIBRARY
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-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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------------------------------------------------------------------------------
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-- Author : Alexis Jeandet
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-- Mail : alexis.jeandet@lpp.polytechnique.fr
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------------------------------------------------------------------------------
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-- APB_FIFO.vhd
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library ieee;
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use ieee.std_logic_1164.all;
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use IEEE.numeric_std.all;
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library techmap;
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use techmap.gencomp.all;
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library grlib;
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use grlib.amba.all;
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use grlib.stdlib.all;
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use grlib.devices.all;
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library lpp;
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use lpp.lpp_amba.all;
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use lpp.apb_devices_list.all;
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use lpp.lpp_memory.all;
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use lpp.iir_filter.all;
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entity APB_FIFO is
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generic (
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tech : integer := apa3;
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pindex : integer := 0;
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paddr : integer := 0;
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pmask : integer := 16#fff#;
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pirq : integer := 0;
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abits : integer := 8;
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FifoCnt : integer := 2;
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Data_sz : integer := 16;
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Addr_sz : integer := 9;
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Enable_ReUse : std_logic := '0';
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Mem_use : integer := use_RAM;
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R : integer := 1;
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W : integer := 1
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);
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port (
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clk : in std_logic; --! Horloge du composant
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rst : in std_logic; --! Reset general du composant
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rclk : in std_logic;
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wclk : in std_logic;
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ReUse : in std_logic_vector(FifoCnt-1 downto 0);
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REN : in std_logic_vector(FifoCnt-1 downto 0); --! Instruction de lecture en m�moire
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WEN : in std_logic_vector(FifoCnt-1 downto 0); --! Instruction d'�criture en m�moire
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Empty : out std_logic_vector(FifoCnt-1 downto 0); --! Flag, M�moire vide
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Full : out std_logic_vector(FifoCnt-1 downto 0); --! Flag, M�moire pleine
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RDATA : out std_logic_vector((FifoCnt*Data_sz)-1 downto 0); --! Registre de donn�es en entr�e
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WDATA : in std_logic_vector((FifoCnt*Data_sz)-1 downto 0); --! Registre de donn�es en sortie
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WADDR : out std_logic_vector((FifoCnt*Addr_sz)-1 downto 0); --! Registre d'addresse (�criture)
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RADDR : out std_logic_vector((FifoCnt*Addr_sz)-1 downto 0); --! Registre d'addresse (lecture)
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apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus
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apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
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);
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end entity;
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architecture ar_APB_FIFO of APB_FIFO is
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constant REVISION : integer := 1;
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constant pconfig : apb_config_type := (
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0 => ahb_device_reg (VENDOR_LPP, LPP_FIFO_PID, 0, REVISION, 0),
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1 => apb_iobar(paddr, pmask));
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type FIFO_ctrlr_Reg is record
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FIFO_Ctrl : std_logic_vector(31 downto 0);
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FIFO_Wdata : std_logic_vector(Data_sz-1 downto 0);
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FIFO_Rdata : std_logic_vector(Data_sz-1 downto 0);
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end record;
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type FIFO_ctrlr_Reg_Vec is array(FifoCnt-1 downto 0) of FIFO_ctrlr_Reg;
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type fifodatabus is array(FifoCnt-1 downto 0) of std_logic_vector(Data_sz-1 downto 0);
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type fifoaddressbus is array(FifoCnt-1 downto 0) of std_logic_vector(Addr_sz-1 downto 0);
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signal Rec : FIFO_ctrlr_Reg_Vec;
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signal PRdata : std_logic_vector(31 downto 0);
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signal FIFO_ID : std_logic_vector(31 downto 0);
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signal autoloaded : std_logic_vector(FifoCnt-1 downto 0);
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signal sFull : std_logic_vector(FifoCnt-1 downto 0);
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signal sEmpty : std_logic_vector(FifoCnt-1 downto 0);
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signal sEmpty_d : std_logic_vector(FifoCnt-1 downto 0);
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signal sWen : std_logic_vector(FifoCnt-1 downto 0);
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signal sRen : std_logic_vector(FifoCnt-1 downto 0);
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signal sRclk : std_logic;
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signal sWclk : std_logic;
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signal sWen_APB : std_logic_vector(FifoCnt-1 downto 0);
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signal sRen_APB : std_logic_vector(FifoCnt-1 downto 0);
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signal sRDATA : fifodatabus;
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signal sWDATA : fifodatabus;
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signal sWADDR : fifoaddressbus;
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signal sRADDR : fifoaddressbus;
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signal sReUse : std_logic_vector(FifoCnt-1 downto 0);
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signal sReUse_APB : std_logic_vector(FifoCnt-1 downto 0);
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signal regDataValid : std_logic_vector(FifoCnt-1 downto 0);
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signal regData : fifodatabus;
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signal regREN : std_logic_vector(FifoCnt-1 downto 0);
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type state_t is (idle,Read);
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signal fiforeadfsmst : state_t;
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begin
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FIFO_ID(3 downto 0) <= std_logic_vector(to_unsigned(FifoCnt,4));
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FIFO_ID(15 downto 8) <= std_logic_vector(to_unsigned(Data_sz,8));
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FIFO_ID(23 downto 16) <= std_logic_vector(to_unsigned(Addr_sz,8));
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Writeint : if W /= 0 generate
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FIFO_ID(4) <= '1';
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sWen <= sWen_APB;
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sReUse <= sReUse_APB;
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sWclk <= clk;
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Wrapb: for i in 0 to FifoCnt-1 generate
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sWDATA(i) <= Rec(i).FIFO_Wdata;
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end generate;
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end generate;
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Writeext : if W = 0 generate
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FIFO_ID(4) <= '0';
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sWen <= WEN;
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sReUse <= ReUse;
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sWclk <= Wclk;
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Wrext: for i in 0 to FifoCnt-1 generate
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sWDATA(i) <= WDATA((Data_sz*(i+1)-1) downto (Data_sz)*i);
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end generate;
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end generate;
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Readint : if R /= 0 generate
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FIFO_ID(5) <= '1';
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sRen <= sRen_APB;
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srclk <= clk;
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Rdapb: for i in 0 to FifoCnt-1 generate
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Rec(i).FIFO_Rdata <= sRDATA(i);
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end generate;
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end generate;
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Readext : if R = 0 generate
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FIFO_ID(5) <= '0';
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sRen <= REN;
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srclk <= rclk;
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Drext: for i in 0 to FifoCnt-1 generate
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RDATA((Data_sz*(i+1))-1 downto (Data_sz)*i) <= sRDATA(i);
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end generate;
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end generate;
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ctrlregs: for i in 0 to FifoCnt-1 generate
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RADDR((Addr_sz*(i+1))-1 downto (Addr_sz)*i) <= sRADDR(i);
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WADDR((Addr_sz*(i+1))-1 downto (Addr_sz)*i) <= sWADDR(i);
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Rec(i).FIFO_Ctrl(16) <= sFull(i);
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sReUse_APB(i) <= Rec(i).FIFO_Ctrl(1);
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Rec(i).FIFO_Ctrl(3 downto 2) <= "00";
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Rec(i).FIFO_Ctrl(19 downto 17) <= "000";
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Rec(i).FIFO_Ctrl(Addr_sz+3 downto 4) <= sRADDR(i);
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Rec(i).FIFO_Ctrl((Addr_sz+19) downto 20) <= sWADDR(i);
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end generate;
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Empty <= sEmpty;
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Full <= sFull;
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fifos: for i in 0 to FifoCnt-1 generate
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FIFO0 : lpp_fifo
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generic map (tech,Mem_use,Enable_ReUse,Data_sz,Addr_sz)
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port map(rst,sReUse(i),srclk,sRen(i),sRDATA(i),sEmpty(i),sRADDR(i),swclk,sWen(i),sWDATA(i),sFull(i),sWADDR(i));
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end generate;
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process(rst,clk)
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begin
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if(rst='0')then
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rstloop1: for i in 0 to FifoCnt-1 loop
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Rec(i).FIFO_Wdata <= (others => '0');
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Rec(i).FIFO_Ctrl(1) <= '0'; -- ReUse
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sWen_APB(i) <= '1';
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end loop;
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elsif(clk'event and clk='1')then
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--APB Write OP
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if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
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writelp: for i in 0 to FifoCnt-1 loop
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if(conv_integer(apbi.paddr(abits-1 downto 2))=((2*i)+1)) then
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Rec(i).FIFO_Ctrl(1) <= apbi.pwdata(1);
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elsif(conv_integer(apbi.paddr(abits-1 downto 2))=((2*i)+2)) then
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Rec(i).FIFO_Wdata <= apbi.pwdata(Data_sz-1 downto 0);
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sWen_APB(i) <= '0';
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end if;
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end loop;
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else
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sWen_APB <= (others =>'1');
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end if;
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--APB Read OP
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if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
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if(apbi.paddr(abits-1 downto 2)="000000") then
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PRdata <= FIFO_ID;
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else
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readlp: for i in 0 to FifoCnt-1 loop
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if(conv_integer(apbi.paddr(abits-1 downto 2))=((2*i)+1)) then
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PRdata <= Rec(i).FIFO_Ctrl;
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elsif(conv_integer(apbi.paddr(abits-1 downto 2))=((2*i)+2)) then
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PRdata(Data_sz-1 downto 0) <= Rec(i).FIFO_rdata;
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end if;
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end loop;
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end if;
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end if;
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end if;
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apbo.pconfig <= pconfig;
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end process;
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apbo.prdata <= PRdata when apbi.penable = '1';
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process(rst,clk)
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begin
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if(rst='0')then
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fiforeadfsmst <= idle;
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rstloop: for i in 0 to FifoCnt-1 loop
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sRen_APB(i) <= '1';
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autoloaded(i) <= '1';
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Rec(i).FIFO_Ctrl(0) <= sEmpty(i);
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end loop;
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elsif clk'event and clk = '1' then
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sEmpty_d <= sEmpty;
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case fiforeadfsmst is
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when idle =>
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idlelp: for i in 0 to FifoCnt-1 loop
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if((sEmpty_d(i) = '1' and sEmpty(i) = '0' and autoloaded(i) = '1')or((conv_integer(apbi.paddr(abits-1 downto 2))=((2*i)+2)) and (apbi.psel(pindex)='1' and apbi.penable='1' and apbi.pwrite='0'))) then
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if(sEmpty_d(i) = '1' and sEmpty(i) = '0') then
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autoloaded(i) <= '0';
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else
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autoloaded(i) <= '1';
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end if;
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sRen_APB(i) <= '0';
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fiforeadfsmst <= read;
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Rec(i).FIFO_Ctrl(0) <= sEmpty(i);
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else
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sRen_APB(i) <= '1';
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end if;
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end loop;
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when read =>
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sRen_APB <= (others => '1');
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fiforeadfsmst <= idle;
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when others =>
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fiforeadfsmst <= idle;
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end case;
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end if;
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end process;
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end ar_APB_FIFO;
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