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------------------------------------------------------------------------------
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-- This file is a part of the LPP VHDL IP LIBRARY
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-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-------------------------------------------------------------------------------
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-- Author : Jean-christophe Pellion
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-- Mail : jean-christophe.pellion@lpp.polytechnique.fr
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-- jean-christophe.pellion@easii-ic.com
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----------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE ieee.numeric_std.ALL;
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LIBRARY grlib;
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USE grlib.amba.ALL;
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USE grlib.stdlib.ALL;
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USE grlib.devices.ALL;
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USE GRLIB.DMA2AHB_Package.ALL;
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LIBRARY lpp;
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USE lpp.lpp_amba.ALL;
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USE lpp.apb_devices_list.ALL;
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USE lpp.lpp_memory.ALL;
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LIBRARY techmap;
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USE techmap.gencomp.ALL;
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ENTITY lpp_dma_send_1word IS
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PORT (
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-- AMBA AHB system signals
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HCLK : IN STD_ULOGIC;
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HRESETn : IN STD_ULOGIC;
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-- DMA
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DMAIn : OUT DMA_In_Type;
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DMAOut : IN DMA_OUt_Type;
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--
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send : IN STD_LOGIC;
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address : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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ren : OUT STD_LOGIC;
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--
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send_ok : OUT STD_LOGIC;
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send_ko : OUT STD_LOGIC
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);
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END lpp_dma_send_1word;
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ARCHITECTURE beh OF lpp_dma_send_1word IS
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TYPE state_fsm_send_1word IS (IDLE, REQUEST_BUS, SEND_DATA, ERROR0, ERROR1);
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SIGNAL state : state_fsm_send_1word;
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BEGIN -- beh
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DMAIn.Reset <= '0';
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DMAIn.Address <= address;
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DMAIn.Data <= data;
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DMAIn.Beat <= (OTHERS => '0');
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DMAIn.Size <= HSIZE32;
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DMAIn.Burst <= '0';
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PROCESS (HCLK, HRESETn)
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BEGIN -- PROCESS
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IF HRESETn = '0' THEN -- asynchronous reset (active low)
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state <= IDLE;
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DMAIn.Request <= '0';
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DMAIn.Store <= '0';
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send_ok <= '0';
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send_ko <= '0';
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DMAIn.Lock <= '0';
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ren <= '1';
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ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
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ren <= '1';
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CASE state IS
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WHEN IDLE =>
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DMAIn.Store <= '1';
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DMAIn.Request <= '0';
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send_ok <= '0';
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send_ko <= '0';
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DMAIn.Lock <= '0';
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IF send = '1' THEN
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DMAIn.Request <= '1';
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DMAIn.Lock <= '1';
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state <= REQUEST_BUS;
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END IF;
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WHEN REQUEST_BUS =>
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IF DMAOut.Grant = '1' THEN
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DMAIn.Request <= '0';
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DMAIn.Store <= '0';
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state <= SEND_DATA;
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ren <= '0';
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END IF;
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WHEN SEND_DATA =>
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IF DMAOut.Fault = '1' THEN
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DMAIn.Request <= '0';
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DMAIn.Store <= '0';
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state <= ERROR0;
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ELSIF DMAOut.Ready = '1' THEN
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DMAIn.Request <= '0';
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DMAIn.Store <= '0';
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send_ok <= '1';
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send_ko <= '0';
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state <= IDLE;
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END IF;
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WHEN ERROR0 =>
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state <= ERROR1;
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WHEN ERROR1 =>
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send_ok <= '0';
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send_ko <= '1';
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state <= IDLE;
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WHEN OTHERS => NULL;
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END CASE;
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END IF;
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END PROCESS;
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END beh;
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