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------------------------------------------------------------------------------
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-- This file is a part of the LPP VHDL IP LIBRARY
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-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-------------------------------------------------------------------------------
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-- Author : Jean-christophe Pellion
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-- Mail : jean-christophe.pellion@lpp.polytechnique.fr
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-- jean-christophe.pellion@easii-ic.com
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-------------------------------------------------------------------------------
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-- 1.0 - initial version
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-------------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE ieee.numeric_std.ALL;
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LIBRARY grlib;
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USE grlib.amba.ALL;
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USE grlib.stdlib.ALL;
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USE grlib.devices.ALL;
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LIBRARY lpp;
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USE lpp.lpp_amba.ALL;
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USE lpp.apb_devices_list.ALL;
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USE lpp.lpp_memory.ALL;
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USE lpp.lpp_dma_pkg.ALL;
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USE lpp.general_purpose.ALL;
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--USE lpp.lpp_waveform_pkg.ALL;
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LIBRARY techmap;
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USE techmap.gencomp.ALL;
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ENTITY lpp_dma_SEND16B_FIFO2DMA IS
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GENERIC (
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hindex : INTEGER := 2;
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vendorid : IN INTEGER := 0;
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deviceid : IN INTEGER := 0;
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version : IN INTEGER := 0
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);
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PORT (
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clk : IN STD_LOGIC;
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rstn : IN STD_LOGIC;
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-- AMBA AHB Master Interface
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AHB_Master_In : IN AHB_Mst_In_Type;
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AHB_Master_Out : OUT AHB_Mst_Out_Type;
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-- FIFO Interface
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ren : OUT STD_LOGIC;
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data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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-- Controls
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send : IN STD_LOGIC;
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valid_burst : IN STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
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done : OUT STD_LOGIC;
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address : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
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);
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END;
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ARCHITECTURE Behavioral OF lpp_dma_SEND16B_FIFO2DMA IS
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CONSTANT HConfig : AHB_Config_Type := (
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0 => ahb_device_reg(vendorid, deviceid, 0, version, 0),
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OTHERS => (OTHERS => '0'));
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TYPE AHB_DMA_FSM_STATE IS (IDLE, s_INIT_TRANS, s_ARBITER ,s_CTRL, s_CTRL_DATA, s_DATA);
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SIGNAL state : AHB_DMA_FSM_STATE;
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SIGNAL address_counter_reg : STD_LOGIC_VECTOR(3 DOWNTO 0);
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SIGNAL data_window : STD_LOGIC;
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SIGNAL ctrl_window : STD_LOGIC;
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SIGNAL data_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
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SIGNAL HREADY_pre : STD_LOGIC;
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SIGNAL HREADY_falling : STD_LOGIC;
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SIGNAL inhib_ren : STD_LOGIC;
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BEGIN
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-----------------------------------------------------------------------------
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AHB_Master_Out.HCONFIG <= HConfig;
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AHB_Master_Out.HSIZE <= "010"; --WORDS 32b
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AHB_Master_Out.HINDEX <= hindex;
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AHB_Master_Out.HPROT <= "0011"; --DATA ACCESS and PRIVILEDGED ACCESS
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AHB_Master_Out.HIRQ <= (OTHERS => '0');
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AHB_Master_Out.HBURST <= "111"; -- INCR --"111"; --INCR16
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AHB_Master_Out.HWRITE <= '1';
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--AHB_Master_Out.HTRANS <= HTRANS_NONSEQ WHEN ctrl_window = '1' OR data_window = '1' ELSE HTRANS_IDLE;
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--AHB_Master_Out.HBUSREQ <= bus_request;
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--AHB_Master_Out.HLOCK <= data_window;
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--bus_request <= '0' WHEN address_counter_reg = "1111" AND AHB_Master_In.HREADY = '1' ELSE
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-- '1' WHEN ctrl_window = '1' ELSE
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-- '0';
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--bus_lock <= '0' WHEN address_counter_reg = "1111" ELSE
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-- '1' WHEN ctrl_window = '1' ELSE '0';
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-----------------------------------------------------------------------------
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AHB_Master_Out.HADDR <= address(31 DOWNTO 6) & address_counter_reg & "00";
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AHB_Master_Out.HWDATA <= ahbdrivedata(data) WHEN AHB_Master_In.HREADY = '1' ELSE ahbdrivedata(data_reg);
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-----------------------------------------------------------------------------
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--ren <= NOT ((AHB_Master_In.HGRANT(hindex) OR LAST_READ ) AND AHB_Master_In.HREADY );
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--ren <= NOT beat;
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-----------------------------------------------------------------------------
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HREADY_falling <= inhib_ren WHEN AHB_Master_In.HREADY = '0' AND HREADY_pre = '1' ELSE '1';
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PROCESS (clk, rstn)
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BEGIN -- PROCESS
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IF rstn = '0' THEN -- asynchronous reset (active low)
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state <= IDLE;
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done <= '0';
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ren <= '1';
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address_counter_reg <= (OTHERS => '0');
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AHB_Master_Out.HTRANS <= HTRANS_IDLE;
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AHB_Master_Out.HBUSREQ <= '0';
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AHB_Master_Out.HLOCK <= '0';
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data_reg <= (OTHERS => '0');
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HREADY_pre <= '0';
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inhib_ren <= '0';
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ELSIF clk'event AND clk = '1' THEN -- rising clock edge
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HREADY_pre <= AHB_Master_In.HREADY;
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IF AHB_Master_In.HREADY = '1' AND AHB_Master_In.HGRANT(hindex) = '1' THEN
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data_reg <= data;
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END IF;
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done <= '0';
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ren <= '1';
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inhib_ren <= '0';
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CASE state IS
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WHEN IDLE =>
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AHB_Master_Out.HBUSREQ <= '0';
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AHB_Master_Out.HLOCK <= '0';
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AHB_Master_Out.HTRANS <= HTRANS_IDLE;
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address_counter_reg <= (OTHERS => '0');
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IF send = '1' THEN
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state <= s_INIT_TRANS;
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END IF;
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WHEN s_INIT_TRANS =>
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AHB_Master_Out.HBUSREQ <= '1';
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AHB_Master_Out.HLOCK <= '1';
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AHB_Master_Out.HTRANS <= HTRANS_IDLE;
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state <= s_ARBITER;
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WHEN s_ARBITER =>
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AHB_Master_Out.HBUSREQ <= '1';
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AHB_Master_Out.HLOCK <= '1';
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AHB_Master_Out.HTRANS <= HTRANS_IDLE;
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address_counter_reg <= (OTHERS => '0');
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IF AHB_Master_In.HREADY = '1' AND AHB_Master_In.HGRANT(hindex) = '1' THEN
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AHB_Master_Out.HTRANS <= HTRANS_IDLE;
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state <= s_CTRL;
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END IF;
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WHEN s_CTRL =>
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inhib_ren <= '1';
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AHB_Master_Out.HBUSREQ <= '1';
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AHB_Master_Out.HLOCK <= '1';
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AHB_Master_Out.HTRANS <= HTRANS_NONSEQ;
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IF AHB_Master_In.HREADY = '1' AND AHB_Master_In.HGRANT(hindex) = '1' THEN
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--AHB_Master_Out.HTRANS <= HTRANS_SEQ;
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state <= s_CTRL_DATA;
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--ren <= '0';
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END IF;
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WHEN s_CTRL_DATA =>
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AHB_Master_Out.HBUSREQ <= '1';
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AHB_Master_Out.HLOCK <= '1';
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AHB_Master_Out.HTRANS <= HTRANS_SEQ;
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IF AHB_Master_In.HREADY = '1' AND AHB_Master_In.HGRANT(hindex) = '1' THEN
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address_counter_reg <= STD_LOGIC_VECTOR(UNSIGNED(address_counter_reg) + 1);
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END IF;
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IF address_counter_reg = "1111" AND AHB_Master_In.HREADY = '1' THEN
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AHB_Master_Out.HBUSREQ <= '0';
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AHB_Master_Out.HLOCK <= '1';--'0';
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AHB_Master_Out.HTRANS <= HTRANS_IDLE;
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state <= s_DATA;
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END IF;
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ren <= HREADY_falling;
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--IF AHB_Master_In.HREADY = '1' AND AHB_Master_In.HGRANT(hindex) = '1' AND address_counter_reg /= "1111" THEN
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-- ren <= '0';
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--END IF;
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WHEN s_DATA =>
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ren <= HREADY_falling;
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AHB_Master_Out.HBUSREQ <= '0';
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--AHB_Master_Out.HLOCK <= '0';
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AHB_Master_Out.HTRANS <= HTRANS_IDLE;
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IF AHB_Master_In.HREADY = '1' THEN
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AHB_Master_Out.HLOCK <= '0';
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state <= IDLE;
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done <= '1';
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END IF;
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WHEN OTHERS => NULL;
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END CASE;
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END IF;
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END PROCESS;
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ctrl_window <= '1' WHEN state = s_CTRL OR state = s_CTRL_DATA ELSE '0';
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data_window <= '1' WHEN state = s_CTRL_DATA OR state = s_DATA ELSE '0';
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-----------------------------------------------------------------------------
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--ren <= NOT(AHB_Master_In.HREADY) WHEN state = s_CTRL_DATA ELSE '1';
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-----------------------------------------------------------------------------
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--PROCESS (clk, rstn)
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--BEGIN -- PROCESS
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-- IF rstn = '0' THEN -- asynchronous reset (active low)
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-- address_counter_reg <= (OTHERS => '0');
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-- ELSIF clk'event AND clk = '1' THEN -- rising clock edge
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-- address_counter_reg <= address_counter;
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-- END IF;
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--END PROCESS;
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--address_counter <= STD_LOGIC_VECTOR(UNSIGNED(address_counter_reg) + 1) WHEN data_window = '1' AND AHB_Master_In.HREADY = '1' AND AHB_Master_In.HGRANT(hindex) = '1' ELSE
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-- address_counter_reg;
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-----------------------------------------------------------------------------
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END Behavioral;
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