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------------------------------------------------------------------------------
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-- This file is a part of the LPP VHDL IP LIBRARY
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-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-------------------------------------------------------------------------------
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-- Author : Jean-christophe Pellion
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-- Mail : jean-christophe.pellion@lpp.polytechnique.fr
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-- jean-christophe.pellion@easii-ic.com
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----------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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LIBRARY grlib;
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USE grlib.amba.ALL;
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USE grlib.stdlib.ALL;
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USE grlib.devices.ALL;
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USE GRLIB.DMA2AHB_Package.ALL;
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LIBRARY lpp;
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USE lpp.lpp_amba.ALL;
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USE lpp.apb_devices_list.ALL;
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USE lpp.lpp_memory.ALL;
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LIBRARY techmap;
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USE techmap.gencomp.ALL;
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ENTITY fifo_test_dma IS
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GENERIC (
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tech : INTEGER := apa3;
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pindex : INTEGER := 0;
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paddr : INTEGER := 0;
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pmask : INTEGER := 16#fff#
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);
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PORT (
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-- AMBA AHB system signals
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HCLK : IN STD_ULOGIC;
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HRESETn : IN STD_ULOGIC;
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-- AMBA APB Slave Interface
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apbi : IN apb_slv_in_type;
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apbo : OUT apb_slv_out_type;
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-- FIFO Read interface
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fifo_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
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fifo_empty : OUT STD_LOGIC;
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fifo_ren : IN STD_LOGIC;
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-- header
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header : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
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header_val : OUT STD_LOGIC;
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header_ack : IN STD_LOGIC
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);
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END;
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ARCHITECTURE Behavioral OF fifo_test_dma IS
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CONSTANT REVISION : INTEGER := 1;
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CONSTANT pconfig : apb_config_type := (
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0 => ahb_device_reg (VENDOR_LPP, 0 , 0, REVISION, 0),
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1 => apb_iobar(paddr, pmask));
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TYPE lpp_test_dma_regs IS RECORD
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tt : STD_LOGIC;
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END RECORD;
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SIGNAL reg : lpp_test_dma_regs;
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SIGNAL prdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
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-----------------------------------------------------------------------------
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SIGNAL fifo_empty_s : STD_LOGIC;
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SIGNAL fifo_raddr : STD_LOGIC_VECTOR(7 DOWNTO 0);
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SIGNAL fifo_wen : STD_LOGIC;
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SIGNAL fifo_wdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
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SIGNAL fifo_full : STD_LOGIC;
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SIGNAL fifo_waddr : STD_LOGIC_VECTOR(7 DOWNTO 0);
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-----------------------------------------------------------------------------
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SIGNAL fifo_nb_data : STD_LOGIC_VECTOR( 7 DOWNTO 0);
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SIGNAL fifo_nb_data_s : STD_LOGIC_VECTOR( 7 DOWNTO 0);
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-----------------------------------------------------------------------------
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SIGNAL header_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
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SIGNAL header_val_s : STD_LOGIC;
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BEGIN
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lpp_fifo_i : lpp_fifo
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GENERIC MAP (
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tech => tech,
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Enable_ReUse => '0',
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DataSz => 32,
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abits => 8)
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PORT MAP (
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rstn => HRESETn,
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ReUse => '0',
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rclk => HCLK,
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ren => fifo_ren,
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rdata => fifo_data,
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empty => fifo_empty_s,
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raddr => fifo_raddr,
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wclk => HCLK,
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wen => fifo_wen,
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wdata => fifo_wdata,
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full => fifo_full,
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waddr => fifo_waddr); -- OUT
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fifo_nb_data_s(7) <= '1' WHEN (fifo_waddr < fifo_raddr) ELSE '0';
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fifo_nb_data_s(6 DOWNTO 0) <= (OTHERS => '0');
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fifo_nb_data <= (fifo_waddr - fifo_raddr) + fifo_nb_data_s;
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fifo_empty <= fifo_empty_s;
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header <= header_s;
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header_val <= header_val_s;
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-----------------------------------------------------------------------------
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apb_reg_p : PROCESS (HCLK, HRESETn)
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VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2);
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BEGIN -- PROCESS lpp_dma_top
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IF HRESETn = '0' THEN -- asynchronous reset (active low)
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prdata <= (OTHERS => '0');
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fifo_wdata <= (OTHERS => '0');
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fifo_wen <= '1';
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header_val_s <= '0';
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header_s <= (OTHERS => '0');
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ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
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paddr := "000000";
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paddr(7 DOWNTO 2) := apbi.paddr(7 DOWNTO 2);
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fifo_wen <= '1';
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header_val_s <= header_val_s AND (NOT header_ack);
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IF (apbi.psel(pindex)) = '1' THEN
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-- APB DMA READ --
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CASE paddr(7 DOWNTO 2) IS
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WHEN "000000" => prdata( 7 DOWNTO 0) <= fifo_waddr;
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prdata(15 DOWNTO 8) <= fifo_raddr;
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prdata(23 DOWNTO 16) <= fifo_nb_data;
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prdata(24) <= fifo_full;
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prdata(25) <= fifo_empty_s;
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WHEN "000001" => prdata(31 DOWNTO 0) <= header_s;
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WHEN OTHERS => prdata <= (OTHERS => '0');
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END CASE;
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IF (apbi.pwrite AND apbi.penable) = '1' THEN
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-- APB DMA WRITE --
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CASE paddr(7 DOWNTO 2) IS
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WHEN "000000" => fifo_wdata <= apbi.pwdata;
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fifo_wen <= '0';
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WHEN "000001" => header_s <= apbi.pwdata;
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header_val_s <= '1';
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WHEN OTHERS => NULL;
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END CASE;
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END IF;
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END IF;
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END IF;
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END PROCESS apb_reg_p;
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apbo.pirq <= (OTHERS => '0');
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apbo.pindex <= pindex;
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apbo.pconfig <= pconfig;
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apbo.prdata <= prdata;
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END Behavioral;
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