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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE ieee.numeric_std.ALL;
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LIBRARY lpp;
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USE lpp.lpp_ad_conv.ALL;
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USE lpp.iir_filter.ALL;
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USE lpp.FILTERcfg.ALL;
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USE lpp.lpp_memory.ALL;
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--USE lpp.lpp_waveform_pkg.ALL;
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USE lpp.lpp_dma_pkg.ALL;
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--USE lpp.lpp_top_lfr_pkg.ALL;
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--USE lpp.lpp_lfr_pkg.ALL;
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USE lpp.general_purpose.ALL;
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LIBRARY techmap;
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USE techmap.gencomp.ALL;
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LIBRARY grlib;
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USE grlib.amba.ALL;
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USE grlib.stdlib.ALL;
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USE grlib.devices.ALL;
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USE GRLIB.DMA2AHB_Package.ALL;
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ENTITY DMA_SubSystem_MUX IS
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PORT (
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clk : IN STD_LOGIC;
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rstn : IN STD_LOGIC;
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run : IN STD_LOGIC;
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--
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fifo_grant : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
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fifo_data : IN STD_LOGIC_VECTOR(32*5-1 DOWNTO 0); --
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fifo_address : IN STD_LOGIC_VECTOR(32*5-1 DOWNTO 0); --
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fifo_ren : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); --
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fifo_burst_done : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
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--
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dma_send : OUT STD_LOGIC;
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dma_valid_burst : OUT STD_LOGIC; --
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dma_address : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --
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dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --
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dma_ren : IN STD_LOGIC; --
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dma_done : IN STD_LOGIC; --
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--
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grant_error : OUT STD_LOGIC --
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);
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END DMA_SubSystem_MUX;
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ARCHITECTURE beh OF DMA_SubSystem_MUX IS
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SIGNAL channel_ongoing : STD_LOGIC_VECTOR(4 DOWNTO 0);
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SIGNAL one_grant : STD_LOGIC;
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SIGNAL more_than_one_grant : STD_LOGIC;
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BEGIN
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one_grant <= '0' WHEN fifo_grant = "00000" ELSE '1';
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more_than_one_grant <= '0' WHEN fifo_grant = "00000" OR
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fifo_grant = "00001" OR
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fifo_grant = "00010" OR
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fifo_grant = "00100" OR
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fifo_grant = "01000" OR
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fifo_grant = "10000" ELSE '1';
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PROCESS (clk, rstn)
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BEGIN -- PROCESS
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IF rstn = '0' THEN -- asynchronous reset (active low)
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channel_ongoing <= (OTHERS => '0');
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fifo_burst_done <= (OTHERS => '0');
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dma_send <= '0';
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dma_valid_burst <= '0';
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grant_error <= '0';
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ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
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grant_error <= '0';
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IF run = '1' THEN
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IF dma_done = '1' THEN
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fifo_burst_done <= channel_ongoing;
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ELSE
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fifo_burst_done <= (OTHERS => '0');
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END IF;
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IF channel_ongoing = "00000" OR dma_done = '1' THEN
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channel_ongoing <= fifo_grant;
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grant_error <= more_than_one_grant;
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dma_valid_burst <= one_grant;
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dma_send <= one_grant;
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ELSE
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dma_send <= '0';
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END IF;
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ELSE
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channel_ongoing <= (OTHERS => '0');
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fifo_burst_done <= (OTHERS => '0');
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dma_send <= '0';
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dma_valid_burst <= '0';
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END IF;
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END IF;
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END PROCESS;
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-------------------------------------------------------------------------
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all_channel : FOR I IN 4 DOWNTO 0 GENERATE
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fifo_ren(I) <= dma_ren WHEN channel_ongoing(I) = '1' ELSE '1';
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END GENERATE all_channel;
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dma_data <= fifo_data(32*1-1 DOWNTO 32*0) WHEN channel_ongoing(0) = '1' ELSE
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fifo_data(32*2-1 DOWNTO 32*1) WHEN channel_ongoing(1) = '1' ELSE
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fifo_data(32*3-1 DOWNTO 32*2) WHEN channel_ongoing(2) = '1' ELSE
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fifo_data(32*4-1 DOWNTO 32*3) WHEN channel_ongoing(3) = '1' ELSE
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fifo_data(32*5-1 DOWNTO 32*4); --WHEN channel_ongoing(4) = '1' ELSE
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dma_address <= fifo_address(32*1-1 DOWNTO 32*0) WHEN channel_ongoing(0) = '1' ELSE
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fifo_address(32*2-1 DOWNTO 32*1) WHEN channel_ongoing(1) = '1' ELSE
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fifo_address(32*3-1 DOWNTO 32*2) WHEN channel_ongoing(2) = '1' ELSE
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fifo_address(32*4-1 DOWNTO 32*3) WHEN channel_ongoing(3) = '1' ELSE
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fifo_address(32*5-1 DOWNTO 32*4); --WHEN channel_ongoing(4) = '1' ELSE
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END beh;
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