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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE ieee.numeric_std.ALL;
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ENTITY DMA_SubSystem_GestionBuffer IS
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GENERIC (
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BUFFER_ADDR_SIZE : INTEGER := 32;
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BUFFER_LENGTH_SIZE : INTEGER := 26);
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PORT (
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clk : IN STD_LOGIC;
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rstn : IN STD_LOGIC;
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-- run : IN STD_LOGIC;
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--
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buffer_new : IN STD_LOGIC;
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buffer_addr : IN STD_LOGIC_VECTOR(BUFFER_ADDR_SIZE-1 DOWNTO 0);
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buffer_length : IN STD_LOGIC_VECTOR(BUFFER_LENGTH_SIZE-1 DOWNTO 0); --in 64B
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buffer_full : OUT STD_LOGIC;
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buffer_full_err : OUT STD_LOGIC;
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--
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burst_send : IN STD_LOGIC;
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burst_addr : OUT STD_LOGIC_VECTOR(BUFFER_ADDR_SIZE-1 DOWNTO 0)
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);
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END DMA_SubSystem_GestionBuffer;
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ARCHITECTURE beh OF DMA_SubSystem_GestionBuffer IS
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TYPE state_DMA_GestionBuffer IS (IDLE, ON_GOING);
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SIGNAL state : state_DMA_GestionBuffer;
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SIGNAL burst_send_counter : STD_LOGIC_VECTOR(BUFFER_LENGTH_SIZE-1 DOWNTO 0);
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SIGNAL burst_send_counter_add1 : STD_LOGIC_VECTOR(BUFFER_LENGTH_SIZE-1 DOWNTO 0);
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SIGNAL addr_shift : STD_LOGIC_VECTOR(BUFFER_ADDR_SIZE-1 DOWNTO 0);
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BEGIN
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addr_shift <= burst_send_counter & "000000";
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burst_addr <= STD_LOGIC_VECTOR(unsigned(buffer_addr) + unsigned(addr_shift));
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burst_send_counter_add1 <= STD_LOGIC_VECTOR(unsigned(burst_send_counter) + 1);
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PROCESS (clk, rstn)
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BEGIN -- PROCESS
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IF rstn = '0' THEN -- asynchronous reset (active low)
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burst_send_counter <= (OTHERS => '0');
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state <= IDLE;
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buffer_full <= '0';
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buffer_full_err <= '0';
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ELSIF clk'event AND clk = '1' THEN -- rising clock edge
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CASE state IS
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WHEN IDLE =>
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burst_send_counter <= (OTHERS => '0');
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buffer_full_err <= burst_send;
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buffer_full <= '0';
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IF buffer_new = '1' THEN
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state <= ON_GOING;
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END IF;
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WHEN ON_GOING =>
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buffer_full_err <= '0';
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buffer_full <= '0';
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IF burst_send = '1' THEN
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IF unsigned(burst_send_counter_add1) < unsigned(buffer_length) THEN
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burst_send_counter <= burst_send_counter_add1;
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ELSE
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buffer_full <= '1';
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state <= IDLE;
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END IF;
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END IF;
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WHEN OTHERS => NULL;
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END CASE;
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END IF;
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END PROCESS;
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END beh;
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