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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE ieee.numeric_std.ALL;
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LIBRARY lpp;
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USE lpp.apb_devices_list.ALL;
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USE lpp.lpp_ad_conv.ALL;
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USE lpp.iir_filter.ALL;
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USE lpp.FILTERcfg.ALL;
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USE lpp.lpp_memory.ALL;
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--USE lpp.lpp_waveform_pkg.ALL;
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USE lpp.lpp_dma_pkg.ALL;
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--USE lpp.lpp_top_lfr_pkg.ALL;
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--USE lpp.lpp_lfr_pkg.ALL;
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USE lpp.general_purpose.ALL;
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LIBRARY techmap;
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USE techmap.gencomp.ALL;
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LIBRARY grlib;
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USE grlib.amba.ALL;
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USE grlib.stdlib.ALL;
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USE grlib.devices.ALL;
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USE GRLIB.DMA2AHB_Package.ALL;
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ENTITY DMA_SubSystem IS
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GENERIC (
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hindex : INTEGER := 2;
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CUSTOM_DMA : INTEGER := 1);
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PORT (
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clk : IN STD_LOGIC;
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rstn : IN STD_LOGIC;
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run : IN STD_LOGIC;
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-- AHB
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ahbi : IN AHB_Mst_In_Type;
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ahbo : OUT AHB_Mst_Out_Type;
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---------------------------------------------------------------------------
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fifo_burst_valid : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
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fifo_data : IN STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
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fifo_ren : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
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---------------------------------------------------------------------------
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buffer_new : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
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buffer_addr : IN STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
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buffer_length : IN STD_LOGIC_VECTOR(26*5-1 DOWNTO 0);
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buffer_full : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
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buffer_full_err : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
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---------------------------------------------------------------------------
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grant_error : OUT STD_LOGIC;
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---------------------------------------------------------------------------
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debug_vector : OUT STD_LOGIC_VECTOR(8 DOWNTO 0)
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);
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END DMA_SubSystem;
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ARCHITECTURE beh OF DMA_SubSystem IS
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COMPONENT DMA_SubSystem_GestionBuffer
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GENERIC (
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BUFFER_ADDR_SIZE : INTEGER;
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BUFFER_LENGTH_SIZE : INTEGER);
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PORT (
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clk : IN STD_LOGIC;
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rstn : IN STD_LOGIC;
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-- run : IN STD_LOGIC;
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buffer_new : IN STD_LOGIC;
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buffer_addr : IN STD_LOGIC_VECTOR(BUFFER_ADDR_SIZE-1 DOWNTO 0);
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buffer_length : IN STD_LOGIC_VECTOR(BUFFER_LENGTH_SIZE-1 DOWNTO 0);
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buffer_full : OUT STD_LOGIC;
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buffer_full_err : OUT STD_LOGIC;
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burst_send : IN STD_LOGIC;
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burst_addr : OUT STD_LOGIC_VECTOR(BUFFER_ADDR_SIZE-1 DOWNTO 0));
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END COMPONENT;
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COMPONENT DMA_SubSystem_Arbiter
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PORT (
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clk : IN STD_LOGIC;
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rstn : IN STD_LOGIC;
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run : IN STD_LOGIC;
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data_burst_valid : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
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data_burst_valid_grant : OUT STD_LOGIC_VECTOR(4 DOWNTO 0));
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END COMPONENT;
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COMPONENT DMA_SubSystem_MUX
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PORT (
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clk : IN STD_LOGIC;
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rstn : IN STD_LOGIC;
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run : IN STD_LOGIC;
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fifo_grant : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
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fifo_data : IN STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
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fifo_address : IN STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
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fifo_ren : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
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fifo_burst_done : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
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dma_send : OUT STD_LOGIC;
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dma_valid_burst : OUT STD_LOGIC;
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dma_address : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
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dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
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dma_ren : IN STD_LOGIC;
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dma_done : IN STD_LOGIC;
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grant_error : OUT STD_LOGIC);
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END COMPONENT;
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-----------------------------------------------------------------------------
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SIGNAL dma_send : STD_LOGIC;
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SIGNAL dma_valid_burst : STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
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SIGNAL dma_done : STD_LOGIC;
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SIGNAL dma_ren : STD_LOGIC;
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SIGNAL dma_address : STD_LOGIC_VECTOR(31 DOWNTO 0);
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SIGNAL dma_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
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SIGNAL burst_send : STD_LOGIC_VECTOR(4 DOWNTO 0);
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SIGNAL fifo_grant : STD_LOGIC_VECTOR(4 DOWNTO 0);
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SIGNAL fifo_address : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0); --
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SIGNAL ahbo_s : AHB_Mst_Out_Type;
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SIGNAL fifo_ren_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
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BEGIN -- beh
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debug_vector <= fifo_ren_s(0) &
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dma_data(1 DOWNTO 0) &
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ahbi.HREADY &
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ahbo_s.HWDATA(1 DOWNTO 0) &
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ahbi.HGRANT(hindex) &
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ahbo_s.HTRANS(0) &
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ahbo_s.HLOCK;
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ahbo <= ahbo_s;
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fifo_ren <= fifo_ren_s;
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-----------------------------------------------------------------------------
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-- DMA
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-----------------------------------------------------------------------------
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GR_DMA : IF CUSTOM_DMA = 0 GENERATE
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lpp_dma_singleOrBurst_1 : lpp_dma_singleOrBurst
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GENERIC MAP (
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tech => inferred,
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hindex => hindex)
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PORT MAP (
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HCLK => clk,
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HRESETn => rstn,
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run => run,
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AHB_Master_In => ahbi,
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AHB_Master_Out => ahbo_s,
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send => dma_send,
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valid_burst => dma_valid_burst,
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done => dma_done,
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ren => dma_ren,
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address => dma_address,
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data => dma_data);
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END GENERATE GR_DMA;
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LPP_DMA_IP : IF CUSTOM_DMA = 1 GENERATE
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lpp_dma_SEND16B_FIFO2DMA_1 : lpp_dma_SEND16B_FIFO2DMA
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GENERIC MAP (
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hindex => hindex,
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vendorid => VENDOR_LPP,
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deviceid => 10,
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version => 0)
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PORT MAP (
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clk => clk,
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rstn => rstn,
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AHB_Master_In => ahbi,
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AHB_Master_Out => ahbo_s,
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ren => dma_ren,
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data => dma_data,
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send => dma_send,
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valid_burst => dma_valid_burst,
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done => dma_done,
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address => dma_address);
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END GENERATE LPP_DMA_IP;
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-----------------------------------------------------------------------------
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-- RoundRobin Selection Channel For DMA
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-----------------------------------------------------------------------------
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DMA_SubSystem_Arbiter_1: DMA_SubSystem_Arbiter
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PORT MAP (
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clk => clk,
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rstn => rstn,
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run => run,
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data_burst_valid => fifo_burst_valid,
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data_burst_valid_grant => fifo_grant);
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-----------------------------------------------------------------------------
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-- Mux between the channel from Waveform Picker and Spectral Matrix
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-----------------------------------------------------------------------------
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DMA_SubSystem_MUX_1: DMA_SubSystem_MUX
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PORT MAP (
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clk => clk,
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rstn => rstn,
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run => run,
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fifo_grant => fifo_grant,
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fifo_data => fifo_data,
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fifo_address => fifo_address,
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fifo_ren => fifo_ren_s,
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fifo_burst_done => burst_send,
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dma_send => dma_send,
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dma_valid_burst => dma_valid_burst,
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dma_address => dma_address,
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dma_data => dma_data,
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dma_ren => dma_ren,
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dma_done => dma_done,
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grant_error => grant_error);
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-----------------------------------------------------------------------------
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-- GEN ADDR
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-----------------------------------------------------------------------------
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all_buffer : FOR I IN 4 DOWNTO 0 GENERATE
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DMA_SubSystem_GestionBuffer_I : DMA_SubSystem_GestionBuffer
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GENERIC MAP (
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BUFFER_ADDR_SIZE => 32,
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BUFFER_LENGTH_SIZE => 26)
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PORT MAP (
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clk => clk,
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rstn => rstn,
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-- run => run,
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buffer_new => buffer_new(I),
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buffer_addr => buffer_addr(32*(I+1)-1 DOWNTO I*32),
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buffer_length => buffer_length(26*(I+1)-1 DOWNTO I*26),
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buffer_full => buffer_full(I),
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buffer_full_err => buffer_full_err(I),
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burst_send => burst_send(I),
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burst_addr => fifo_address(32*(I+1)-1 DOWNTO 32*I)
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);
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END GENERATE all_buffer;
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END beh;
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