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------------------------------------------------------------------------------
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-- This file is a part of the LPP VHDL IP LIBRARY
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-- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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------------------------------------------------------------------------------
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-- Author : Martin Morlot
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-- Mail : martin.morlot@lpp.polytechnique.fr
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-------------------------------------------------------------------------------
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-- Update : Jean-christophe Pellion
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-- Mail : jean-christophe.pellion@lpp.polytechnique.fr
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------------------------------------------------------------------------------
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LIBRARY IEEE;
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USE IEEE.std_logic_1164.ALL;
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USE IEEE.numeric_std.ALL;
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ENTITY DEMUX IS
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GENERIC(
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Data_sz : INTEGER RANGE 1 TO 32 := 16);
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PORT(
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clk : IN STD_LOGIC;
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rstn : IN STD_LOGIC;
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Read : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
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Load : IN STD_LOGIC;
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EmptyF0 : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
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EmptyF1 : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
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EmptyF2 : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
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DataF0 : IN STD_LOGIC_VECTOR((5*Data_sz)-1 DOWNTO 0);
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DataF1 : IN STD_LOGIC_VECTOR((5*Data_sz)-1 DOWNTO 0);
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DataF2 : IN STD_LOGIC_VECTOR((5*Data_sz)-1 DOWNTO 0);
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WorkFreq : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
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Read_DEMUX : OUT STD_LOGIC_VECTOR(14 DOWNTO 0);
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Empty : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
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Data : OUT STD_LOGIC_VECTOR((5*Data_sz)-1 DOWNTO 0)
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);
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END ENTITY;
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ARCHITECTURE ar_DEMUX OF DEMUX IS
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TYPE etat IS (eX, e0, e1, e2, e3);
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SIGNAL ect : etat;
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SIGNAL load_reg : STD_LOGIC;
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CONSTANT Dummy_Read : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
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SIGNAL Countf0 : INTEGER;
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SIGNAL Countf1 : INTEGER;
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SIGNAL i : INTEGER;
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BEGIN
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PROCESS(clk, rstn)
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BEGIN
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IF(rstn = '0')then
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ect <= e0;
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load_reg <= '0';
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Countf0 <= 0;
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Countf1 <= 0;
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i <= 0;
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ELSIF(clk'EVENT AND clk = '1')then
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load_reg <= Load;
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CASE ect IS
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WHEN e0 =>
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IF(load_reg = '1' AND Load = '0')THEN
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IF(Countf0 = 24)THEN
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Countf0 <= 0;
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ect <= e1;
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ELSE
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Countf0 <= Countf0 + 1;
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ect <= e0;
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END IF;
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END IF;
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WHEN e1 =>
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IF(load_reg = '1' AND Load = '0')THEN
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IF(Countf1 = 74)THEN
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Countf1 <= 0;
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ect <= e2;
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ELSE
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Countf1 <= Countf1 + 1;
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IF(i = 4)THEN
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i <= 0;
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ect <= e0;
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ELSE
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i <= i+1;
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ect <= e1;
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END IF;
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END IF;
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END IF;
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WHEN e2 =>
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IF(load_reg = '1' AND Load = '0')THEN
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IF(i = 4)THEN
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i <= 0;
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ect <= e0;
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ELSE
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i <= i+1;
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ect <= e2;
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END IF;
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END IF;
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WHEN OTHERS =>
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NULL;
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END CASE;
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END IF;
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END PROCESS;
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WITH ect SELECT
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Empty <= EmptyF0 WHEN e0,
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EmptyF1 WHEN e1,
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EmptyF2 WHEN e2,
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(OTHERS => '1') WHEN OTHERS;
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WITH ect SELECT
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Data <= DataF0 WHEN e0,
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DataF1 WHEN e1,
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DataF2 WHEN e2,
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(OTHERS => '0') WHEN OTHERS;
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WITH ect SELECT
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Read_DEMUX <= Dummy_Read & Dummy_Read & Read WHEN e0,
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Dummy_Read & Read & Dummy_Read WHEN e1,
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Read & Dummy_Read & Dummy_Read WHEN e2,
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(OTHERS => '1') WHEN OTHERS;
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WITH ect SELECT
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WorkFreq <= "01" WHEN e0,
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"10" WHEN e1,
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"11" WHEN e2,
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"00" WHEN OTHERS;
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END ARCHITECTURE;
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