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------------------------------------------------------------------------------
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-- This file is a part of the LPP VHDL IP LIBRARY
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-- Copyright (C) 2009 - 2015, Laboratory of Plasmas Physic - CNRS
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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------------------------------------------------------------------------------
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-- Author : Alexis Jeandet
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-- Mail : alexis.jeandet@member.fsf.org
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------------------------------------------------------------------------------
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LIBRARY IEEE;
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USE IEEE.STD_LOGIC_1164.ALL;
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LIBRARY techmap;
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USE techmap.gencomp.ALL;
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LIBRARY lpp;
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USE lpp.lpp_cna.ALL;
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ENTITY lfr_cal_driver IS
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GENERIC(
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tech : INTEGER := 0;
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PRESZ : INTEGER RANGE 1 TO 32 := 4;
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PREMAX : INTEGER := 16#FFFFFF#;
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CPTSZ : INTEGER RANGE 1 TO 32 := 16;
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datawidth : INTEGER := 18;
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abits : INTEGER := 8
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);
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PORT (
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clk : IN STD_LOGIC;
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rstn : IN STD_LOGIC;
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pre : IN STD_LOGIC_VECTOR(PRESZ-1 DOWNTO 0);
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N : IN STD_LOGIC_VECTOR(CPTSZ-1 DOWNTO 0);
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Reload : IN STD_LOGIC;
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DATA_IN : IN STD_LOGIC_VECTOR(datawidth-1 DOWNTO 0);
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WEN : IN STD_LOGIC;
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LOAD_ADDRESSN : IN STD_LOGIC;
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ADDRESS_IN : IN STD_LOGIC_VECTOR(abits-1 DOWNTO 0);
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ADDRESS_OUT : OUT STD_LOGIC_VECTOR(abits-1 DOWNTO 0);
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INTERLEAVED : IN STD_LOGIC;
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DAC_CFG : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
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SYNC : OUT STD_LOGIC;
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DOUT : OUT STD_LOGIC;
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SCLK : OUT STD_LOGIC;
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SMPCLK : OUT STD_LOGIC
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);
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END lfr_cal_driver;
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ARCHITECTURE Behavioral OF lfr_cal_driver IS
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CONSTANT dacresolution : INTEGER := 12;
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SIGNAL RAM_DATA_IN : STD_LOGIC_VECTOR(datawidth-1 DOWNTO 0);
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SIGNAL RAM_WEN : STD_LOGIC;
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SIGNAL RAM_WADDR : STD_LOGIC_VECTOR(abits-1 DOWNTO 0);
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SIGNAL RAM_DATA_OUT : STD_LOGIC_VECTOR(datawidth-1 DOWNTO 0);
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SIGNAL RAM_RADDR : STD_LOGIC_VECTOR(abits-1 DOWNTO 0);
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SIGNAL RAM_REN : STD_LOGIC;
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SIGNAL DAC_DATA : STD_LOGIC_VECTOR(dacresolution-1 DOWNTO 0);
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SIGNAL SMP_CLK : STD_LOGIC;
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SIGNAL DAC_INPUT : STD_LOGIC_VECTOR(15 DOWNTO 0);
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BEGIN
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ADDRESS_OUT <= RAM_WADDR;
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DAC_INPUT <= DAC_CFG & DAC_DATA;
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SMPCLK <= SMP_CLK;
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dac_drv : SPI_DAC_DRIVER
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GENERIC MAP(
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datawidth => 16,
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MSBFIRST => 1
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)
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PORT MAP(
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clk => clk,
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rstn => rstn,
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DATA => DAC_INPUT,
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SMP_CLK => SMP_CLK,
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SYNC => SYNC,
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DOUT => DOUT,
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SCLK => SCLK
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);
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freqGen : dynamic_freq_div
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GENERIC MAP(
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PRESZ => PRESZ,
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PREMAX => PREMAX,
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CPTSZ => CPTSZ
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)
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PORT MAP(clk => clk,
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rstn => rstn,
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pre => pre,
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N => N,
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Reload => Reload,
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clk_out => SMP_CLK
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);
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ramWr : RAM_WRITER
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GENERIC MAP(
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datawidth => datawidth,
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abits => abits
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)
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PORT MAP(
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clk => clk,
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rstn => rstn,
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DATA_IN => DATA_IN,
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DATA_OUT => RAM_DATA_IN,
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WEN_IN => WEN,
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WEN_OUT => RAM_WEN,
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LOAD_ADDRESSN => LOAD_ADDRESSN,
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ADDRESS_IN => ADDRESS_IN,
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ADDRESS_OUT => RAM_WADDR
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);
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ramRd : RAM_READER
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GENERIC MAP(
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datawidth => datawidth,
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dacresolution => dacresolution,
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abits => abits
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)
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PORT MAP(
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clk => clk,
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rstn => rstn,
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DATA_IN => RAM_DATA_OUT,
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ADDRESS => RAM_RADDR,
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REN => RAM_REN,
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DATA_OUT => DAC_DATA,
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SMP_CLK => SMP_CLK,
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INTERLEAVED => INTERLEAVED
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);
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SRAM : syncram_2p
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GENERIC MAP(tech, abits, datawidth)
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PORT MAP(clk, RAM_REN, RAM_RADDR, RAM_DATA_OUT, clk, RAM_WEN, RAM_WADDR, RAM_DATA_IN);
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END Behavioral;
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