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------------------------------------------------------------------------------
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-- This file is a part of the LPP VHDL IP LIBRARY
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-- Copyright (C) 2009 - 2015, Laboratory of Plasmas Physic - CNRS
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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------------------------------------------------------------------------------
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-- Author : Alexis Jeandet
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-- Mail : alexis.jeandet@member.fsf.org
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------------------------------------------------------------------------------
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LIBRARY IEEE;
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USE IEEE.STD_LOGIC_1164.ALL;
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USE IEEE.NUMERIC_STD.ALL;
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ENTITY dynamic_freq_div IS
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GENERIC(
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PRESZ : INTEGER RANGE 1 TO 32 := 4;
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PREMAX : INTEGER := 16#FFFFFF#;
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CPTSZ : INTEGER RANGE 1 TO 32 := 16
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);
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PORT (
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clk : IN STD_LOGIC;
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rstn : IN STD_LOGIC;
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pre : IN STD_LOGIC_VECTOR(PRESZ-1 DOWNTO 0);
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N : IN STD_LOGIC_VECTOR(CPTSZ-1 DOWNTO 0);
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Reload : IN STD_LOGIC;
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clk_out : OUT STD_LOGIC
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);
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END dynamic_freq_div;
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ARCHITECTURE Behavioral OF dynamic_freq_div IS
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CONSTANT prescaller_reg_sz : INTEGER := 2**PRESZ;
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CONSTANT PREMAX_max : STD_LOGIC_VECTOR(PRESZ-1 DOWNTO 0) := (OTHERS => '1');
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SIGNAL cpt_reg : STD_LOGIC_VECTOR(CPTSZ-1 DOWNTO 0) := (OTHERS => '0');
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SIGNAL prescaller_reg : STD_LOGIC_VECTOR(prescaller_reg_sz-1 DOWNTO 0); --:=(others => '0');
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SIGNAL internal_clk : STD_LOGIC := '0';
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SIGNAL internal_clk_reg : STD_LOGIC := '0';
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SIGNAL clk_out_reg : STD_LOGIC := '0';
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BEGIN
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max0 : IF (UNSIGNED(PREMAX_max) < PREMAX) GENERATE
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internal_clk <= prescaller_reg(to_integer(UNSIGNED(pre))) WHEN (to_integer(UNSIGNED(pre)) <= UNSIGNED(PREMAX_max)) ELSE
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prescaller_reg(to_integer(UNSIGNED(PREMAX_max)));
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END GENERATE;
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max1 : IF UNSIGNED(PREMAX_max) > PREMAX GENERATE
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internal_clk <= prescaller_reg(to_integer(UNSIGNED(pre))) WHEN (to_integer(UNSIGNED(pre)) <= PREMAX) ELSE
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prescaller_reg(PREMAX);
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END GENERATE;
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prescaller : PROCESS(rstn, clk)
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BEGIN
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IF rstn = '0' then
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prescaller_reg <= (OTHERS => '0');
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ELSIF clk'EVENT AND clk = '1' THEN
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prescaller_reg <= STD_LOGIC_VECTOR(UNSIGNED(prescaller_reg) + 1);
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END IF;
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END PROCESS;
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clk_out <= clk_out_reg;
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counter : PROCESS(rstn, clk)
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BEGIN
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IF rstn = '0' then
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cpt_reg <= (OTHERS => '0');
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internal_clk_reg <= '0';
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clk_out_reg <= '0';
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ELSIF clk'EVENT AND clk = '1' THEN
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internal_clk_reg <= internal_clk;
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IF Reload = '1' THEN
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clk_out_reg <= '0';
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cpt_reg <= (OTHERS => '0');
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ELSIF (internal_clk = '1' AND internal_clk_reg = '0') THEN
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IF cpt_reg = N THEN
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clk_out_reg <= NOT clk_out_reg;
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cpt_reg <= (OTHERS => '0');
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ELSE
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cpt_reg <= STD_LOGIC_VECTOR(UNSIGNED(cpt_reg) + 1);
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END IF;
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END IF;
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END IF;
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END PROCESS;
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END Behavioral;
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