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------------------------------------------------------------------------------
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-- This file is a part of the LPP VHDL IP LIBRARY
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-- Copyright (C) 2009 - 2015, Laboratory of Plasmas Physic - CNRS
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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------------------------------------------------------------------------------
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-- Author : Alexis Jeandet
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-- Mail : alexis.jeandet@member.fsf.org
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------------------------------------------------------------------------------
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LIBRARY IEEE;
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USE IEEE.STD_LOGIC_1164.ALL;
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USE IEEE.NUMERIC_STD.ALL;
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ENTITY SPI_DAC_DRIVER IS
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GENERIC(
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datawidth : INTEGER := 16;
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MSBFIRST : INTEGER := 1
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);
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PORT (
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clk : IN STD_LOGIC;
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rstn : IN STD_LOGIC;
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DATA : IN STD_LOGIC_VECTOR(datawidth-1 DOWNTO 0);
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SMP_CLK : IN STD_LOGIC;
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SYNC : OUT STD_LOGIC;
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DOUT : OUT STD_LOGIC;
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SCLK : OUT STD_LOGIC
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);
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END ENTITY SPI_DAC_DRIVER;
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ARCHITECTURE behav OF SPI_DAC_DRIVER IS
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SIGNAL DATA_s : STD_LOGIC_VECTOR(datawidth-1 DOWNTO 0) := (OTHERS => '0');
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SIGNAL SMP_CLK_R : STD_LOGIC := '0';
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SIGNAL SMP_CLK_RisingEdge : STD_LOGIC := '0';
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SIGNAL SMP_CLK_RisingEdge_1 : STD_LOGIC := '0';
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SIGNAL SMP_CLK_RisingEdge_2 : STD_LOGIC := '0';
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SIGNAL SHIFTREG : STD_LOGIC_VECTOR(datawidth DOWNTO 0) := (OTHERS => '0');
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SIGNAL shiftcnt : INTEGER := 0;
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SIGNAL shifting : STD_LOGIC := '0';
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SIGNAL SCLK_s : STD_LOGIC;
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BEGIN
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-----------------------------------------------------------------------------
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-- Data Re-Orderng
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-----------------------------------------------------------------------------
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MSB : IF MSBFIRST = 1 GENERATE
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DATA_s <= DATA;
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END GENERATE;
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LSB : IF MSBFIRST = 0 GENERATE
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all_bits: FOR I IN 0 TO datawidth-1 GENERATE
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DATA_s(datawidth-1 - I) <= DATA(I);
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END GENERATE all_bits;
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END GENERATE;
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-----------------------------------------------------------------------------
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--
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-----------------------------------------------------------------------------
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PROCESS(clk, rstn)
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BEGIN
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IF rstn = '0' THEN
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SMP_CLK_R <= '0';
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SMP_CLK_RisingEdge_2 <= '0';
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ELSIF clk'EVENT AND clk = '1' THEN
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SMP_CLK_R <= SMP_CLK;
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SMP_CLK_RisingEdge_2 <= SMP_CLK_RisingEdge_1;
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END IF;
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END PROCESS;
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SMP_CLK_RisingEdge_1 <= '1' WHEN SMP_CLK = '1' AND SMP_CLK_R = '0' ELSE '0';
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SMP_CLK_RisingEdge <= '1' WHEN SMP_CLK_RisingEdge_1 = '1' OR SMP_CLK_RisingEdge_2 = '1' ELSE '0';
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-----------------------------------------------------------------------------
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--
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-----------------------------------------------------------------------------
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SCLK <= SCLK_s;
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DOUT <= SHIFTREG(datawidth);
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PROCESS (clk, rstn)
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BEGIN -- PROCESS
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IF rstn = '0' THEN -- asynchronous reset (active low)
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SCLK_s <= '0';
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ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
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SCLK_s <= NOT SCLK_s;
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END IF;
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END PROCESS;
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PROCESS(clk, rstn)
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BEGIN
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IF rstn = '0' THEN
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shifting <= '0';
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SHIFTREG <= (OTHERS => '0');
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SYNC <= '0';
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shiftcnt <= 0;
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ELSIF clk'EVENT AND clk = '1' THEN
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IF SCLK_s = '0' THEN
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IF SMP_CLK_RisingEdge = '1' THEN
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SYNC <= '1';
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shifting <= '1';
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ELSE
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SYNC <= '0';
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IF shiftcnt = datawidth-1 THEN
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shifting <= '0';
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END IF;
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END IF;
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IF shifting = '1' THEN
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shiftcnt <= shiftcnt + 1;
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SHIFTREG(datawidth DOWNTO 1) <= SHIFTREG (datawidth-1 DOWNTO 0);
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ELSE
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SHIFTREG(datawidth-1 DOWNTO 0) <= DATA_s;
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shiftcnt <= 0;
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END IF;
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END IF;
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END IF;
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END PROCESS;
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END ARCHITECTURE behav;
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