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LIBRARY IEEE;
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USE IEEE.STD_LOGIC_1164.ALL;
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USE IEEE.NUMERIC_STD.ALL;
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LIBRARY lpp;
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USE lpp.lpp_ad_conv.ALL;
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USE lpp.general_purpose.SYNC_FF;
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ENTITY top_ad_conv_ADS7886_v2 IS
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GENERIC(
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ChannelCount : INTEGER := 8;
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SampleNbBits : INTEGER := 14;
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ncycle_cnv_high : INTEGER := 40; -- at least 32 cycles
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ncycle_cnv : INTEGER := 500);
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PORT (
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-- CONV
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cnv_clk : IN STD_LOGIC;
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cnv_rstn : IN STD_LOGIC;
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cnv : OUT STD_LOGIC;
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-- DATA
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clk : IN STD_LOGIC;
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rstn : IN STD_LOGIC;
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sck : OUT STD_LOGIC;
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sdo : IN STD_LOGIC_VECTOR(ChannelCount-1 DOWNTO 0);
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-- SAMPLE
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sample : OUT Samples14v(ChannelCount-1 DOWNTO 0);
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sample_val : OUT STD_LOGIC
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);
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END top_ad_conv_ADS7886_v2;
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ARCHITECTURE ar_top_ad_conv_ADS7886_v2 OF top_ad_conv_ADS7886_v2 IS
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SIGNAL cnv_cycle_counter : INTEGER;
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SIGNAL cnv_s : STD_LOGIC;
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SIGNAL cnv_sync : STD_LOGIC;
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SIGNAL cnv_sync_not : STD_LOGIC;
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SIGNAL sample_adc : Samples(ChannelCount-1 DOWNTO 0);
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SIGNAL sample_val_adc : STD_LOGIC;
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BEGIN
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-----------------------------------------------------------------------------
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-- CONV
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-----------------------------------------------------------------------------
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PROCESS (cnv_clk, cnv_rstn)
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BEGIN -- PROCESS
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IF cnv_rstn = '0' THEN -- asynchronous reset (active low)
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cnv_cycle_counter <= 0;
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cnv_s <= '0';
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ELSIF cnv_clk'EVENT AND cnv_clk = '1' THEN -- rising clock edge
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-- IF cnv_run = '1' THEN
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IF cnv_cycle_counter < ncycle_cnv THEN
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cnv_cycle_counter <= cnv_cycle_counter +1;
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IF cnv_cycle_counter < ncycle_cnv_high THEN
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cnv_s <= '1';
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ELSE
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cnv_s <= '0';
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END IF;
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ELSE
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cnv_s <= '1';
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cnv_cycle_counter <= 0;
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END IF;
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--ELSE
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-- cnv_s <= '0';
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-- cnv_cycle_counter <= 0;
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--END IF;
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END IF;
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END PROCESS;
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cnv <= NOT(cnv_s);
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-----------------------------------------------------------------------------
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-- SYNC CNV
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-----------------------------------------------------------------------------
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SYNC_FF_cnv : SYNC_FF
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GENERIC MAP (
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NB_FF_OF_SYNC => 2)
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PORT MAP (
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clk => clk,
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rstn => rstn,
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A => cnv_s, -- the data fetching begins immediately
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A_sync => cnv_sync);
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-----------------------------------------------------------------------------
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cnv_sync_not <= NOT(cnv_sync);
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ADS7886_drvr_v2_1 : ADS7886_drvr_v2
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GENERIC MAP(
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ChannelCount => 8,
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NbBitsSamples => 16)
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PORT MAP(
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-- CONV --
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cnv_clk => cnv_sync_not,
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cnv_rstn => rstn,
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-- DATA --
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clk => clk, -- master clock, 25 MHz
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rstn => rstn,
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sck => sck,
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sdo => sdo,
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-- SAMPLE --
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sample => sample_adc,
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sample_val => sample_val_adc);
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PROCESS (clk, rstn)
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BEGIN -- PROCESS
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IF rstn = '0' THEN -- asynchronous reset (active low)
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FOR k IN 0 TO ChannelCount-1 LOOP
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sample(k)(13 DOWNTO 0) <= (OTHERS => '0');
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END LOOP;
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sample_val <= '0';
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ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
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IF sample_val_adc = '1' THEN
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FOR k IN 0 TO ChannelCount-1 LOOP
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IF (UNSIGNED(sample_adc(k)(11 DOWNTO 0)) >= 2048) THEN
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sample(k)(13 DOWNTO 0) <= "00" &
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STD_LOGIC_VECTOR(UNSIGNED(sample_adc(k)(11 DOWNTO 0)) - 2048);
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ELSE
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sample(k)(13 DOWNTO 0) <= "11" &
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STD_LOGIC_VECTOR(UNSIGNED(sample_adc(k)(11 DOWNTO 0)) - 2048);
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END IF;
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END LOOP;
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sample_val <= sample_val_adc;
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ELSE
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sample_val <= '0';
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END IF;
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END IF;
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END PROCESS;
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END ar_top_ad_conv_ADS7886_v2;
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