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------------------------------------------------------------------------------
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-- This file is a part of the LPP VHDL IP LIBRARY
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-- Copyright (C) 2013, Laboratory of Plasmas Physic - CNRS
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-------------------------------------------------------------------------------
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-- Author : Alexis Jeandet
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-- Mail : alexis.jeandet@lpp.polytechnique.fr
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-------------------------------------------------------------------------------
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LIBRARY IEEE;
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USE IEEE.STD_LOGIC_1164.ALL;
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LIBRARY lpp;
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USE lpp.lpp_ad_conv.ALL;
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ENTITY RHF1401_drvr IS
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GENERIC(
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ChanelCount : INTEGER := 8);
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PORT (
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cnv_clk : IN STD_LOGIC;
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clk : IN STD_LOGIC;
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rstn : IN STD_LOGIC;
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ADC_data : IN Samples14;
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--ADC_smpclk : OUT STD_LOGIC;
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ADC_nOE : OUT STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0);
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sample : OUT Samples14v(ChanelCount-1 DOWNTO 0);
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sample_val : OUT STD_LOGIC
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);
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END RHF1401_drvr;
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ARCHITECTURE ar_RHF1401_drvr OF RHF1401_drvr IS
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TYPE RHF1401_FSM_STATE IS (idle, output_en, latch, data_valid);
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SIGNAL cnv_clk_reg : STD_LOGIC_VECTOR(1 DOWNTO 0) ;--:= (OTHERS => '0');
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SIGNAL start_readout : STD_LOGIC ;--:= '0';
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SIGNAL state : RHF1401_FSM_STATE ;--:= idle;
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SIGNAL adc_index : INTEGER RANGE 0 TO ChanelCount; -- ChanelCount-1
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SIGNAL ADC_nOE_Reg : STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0);
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SIGNAL ADC_nOE_Reg_Shift : STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0);
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SIGNAL sample_reg : Samples14v(ChanelCount-1 DOWNTO 0);
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BEGIN
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--ADC_smpclk <= cnv_clk;
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ADC_nOE <= ADC_nOE_Reg;
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ADC_nOE_Reg <= ADC_nOE_Reg_Shift WHEN state = output_en ELSE (OTHERS => '1');
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PROCESS(rstn, clk)
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BEGIN
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IF rstn = '0' THEN
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cnv_clk_reg(1 DOWNTO 0) <= (OTHERS => '0');
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start_readout <= '0';
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ELSIF clk'EVENT AND clk = '1' THEN
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cnv_clk_reg(1 DOWNTO 0) <= cnv_clk_reg(0) & cnv_clk;
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IF cnv_clk_reg = "10" AND cnv_clk = '0' THEN
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start_readout <= '1';
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ELSE
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start_readout <= '0';
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END IF;
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END IF;
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END PROCESS;
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PROCESS(rstn, clk)
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BEGIN
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IF rstn = '0' THEN
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state <= idle;
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ADC_nOE_Reg_Shift <= (OTHERS => '1');
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adc_index <= 0;
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sample_val <= '0';
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ELSIF clk'EVENT AND clk = '1' THEN
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CASE state IS
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WHEN idle =>
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adc_index <= 0;
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IF start_readout = '1' THEN
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state <= output_en;
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ADC_nOE_Reg_Shift(0) <= '0';
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ADC_nOE_Reg_Shift(ChanelCount-1 DOWNTO 1) <= (OTHERS => '1');
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END IF;
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sample_val <= '0';
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WHEN output_en =>
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sample_reg(ChanelCount-1) <= ADC_data;
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sample_reg(ChanelCount-2 DOWNTO 0) <= sample_reg(ChanelCount-1 DOWNTO 1);
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ADC_nOE_Reg_Shift(ChanelCount-1 DOWNTO 0) <= ADC_nOE_Reg_Shift(ChanelCount-2 DOWNTO 0) & '1';
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adc_index <= adc_index + 1;
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sample_val <= '0';
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state <= latch;
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WHEN latch =>
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IF(adc_index = ChanelCount) THEN
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state <= data_valid;
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ELSE
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state <= output_en;
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END IF;
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sample_val <= '0';
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WHEN data_valid =>
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sample_val <= '1';
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sample <= sample_reg;
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state <= idle;
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END CASE;
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END IF;
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END PROCESS;
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END ar_RHF1401_drvr;
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