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-- ADS1274_DRIVER.vhd
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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library lpp;
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use lpp.lpp_ad_conv.all;
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use lpp.general_purpose.all;
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entity ADS1278_DRIVER is
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generic(modeCfg : ADS127X_MODE_Type := ADS127X_MODE_low_power; formatCfg : ADS127X_FORMAT_Type := ADS127X_FSYNC_FORMAT);
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port(
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Clk : in std_logic;
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reset : in std_logic;
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SpiClk : out std_logic;
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DIN : in std_logic_vector(7 downto 0);
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Ready : in std_logic;
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Format : out std_logic_vector(2 downto 0);
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Mode : out std_logic_vector(1 downto 0);
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ClkDiv : out std_logic;
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PWDOWN : out std_logic_vector(7 downto 0);
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SmplClk : in std_logic;
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OUT0 : out std_logic_vector(23 downto 0);
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OUT1 : out std_logic_vector(23 downto 0);
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OUT2 : out std_logic_vector(23 downto 0);
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OUT3 : out std_logic_vector(23 downto 0);
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OUT4 : out std_logic_vector(23 downto 0);
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OUT5 : out std_logic_vector(23 downto 0);
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OUT6 : out std_logic_vector(23 downto 0);
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OUT7 : out std_logic_vector(23 downto 0);
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FSynch : out std_logic
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);
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end ADS1278_DRIVER;
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architecture ar_ADS1278_DRIVER of ADS1278_DRIVER is
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signal Vec0,Vec1,Vec2,Vec3,Vec4,Vec5,Vec6,Vec7 : std_logic_vector(23 downto 0);
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signal SmplClk_Reg : std_logic:= '0';
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signal N : integer range 0 to 23*8 := 0;
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signal SPI_CLk : std_logic;
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signal SmplClk_clkd : std_logic:= '0';
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begin
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CLKDIV0 : Clk_Divider2
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generic map(16)
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port map(Clk,SPI_CLk);
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Mode(1) <= modeCfg(1);
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Mode(0) <= modeCfg(0);
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Format(2) <= formatCfg(2);
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Format(1) <= formatCfg(1);
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Format(0) <= formatCfg(0);
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PWDOWN <= (others => '1');
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FSynch <= SmplClk_clkd;
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ClkDiv <= '1';
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SpiClk <= SPI_CLk;
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process(reset,SPI_CLk)
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begin
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if reset = '0' then
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Vec0 <= (others => '0');
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Vec1 <= (others => '0');
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Vec2 <= (others => '0');
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Vec3 <= (others => '0');
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Vec4 <= (others => '0');
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Vec5 <= (others => '0');
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Vec6 <= (others => '0');
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Vec7 <= (others => '0');
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N <= 0;
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elsif SPI_CLk'event and SPI_CLk = '1' then
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-- SmplClk_clkd <= SmplClk;
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-- SmplClk_Reg <= SmplClk_clkd;
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--if ((SmplClk_clkd = '1' and SmplClk_Reg = '0') or (N /= 0)) then
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if ((SmplClk_clkd = '1' and SmplClk_Reg = '0') or (N /= 0)) then
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--Vec0(0) <= DIN(0);
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--Vec1(0) <= DIN(1);
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--Vec2(0) <= DIN(2);
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--Vec3(0) <= DIN(3);
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--Vec0(23 downto 1) <= Vec0(22 downto 0);
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--Vec1(23 downto 1) <= Vec1(22 downto 0);
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--Vec2(23 downto 1) <= Vec2(22 downto 0);
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--Vec3(23 downto 1) <= Vec3(22 downto 0);
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Vec0(0) <= DIN(0);
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Vec0(23 downto 1) <= Vec0(22 downto 0);
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Vec1(0) <= Vec0(23);
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Vec1(23 downto 1) <= Vec1(22 downto 0);
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Vec2(0) <= Vec1(23);
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Vec2(23 downto 1) <= Vec2(22 downto 0);
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Vec3(0) <= Vec2(23);
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Vec3(23 downto 1) <= Vec3(22 downto 0);
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Vec4(0) <= Vec3(23);
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Vec4(23 downto 1) <= Vec4(22 downto 0);
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Vec5(0) <= Vec4(23);
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Vec5(23 downto 1) <= Vec5(22 downto 0);
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Vec6(0) <= Vec5(23);
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Vec6(23 downto 1) <= Vec6(22 downto 0);
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Vec7(0) <= Vec6(23);
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Vec7(23 downto 1) <= Vec7(22 downto 0);
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if N = (23*8) then
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N <= 0;
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else
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N <= N+1;
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end if;
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end if;
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end if;
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end process;
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process(SPI_CLk)
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begin
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if SPI_CLk'event and SPI_CLk ='0' then
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SmplClk_clkd <= SmplClk;
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SmplClk_Reg <= SmplClk_clkd;
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end if;
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end process;
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process(SPI_CLk)
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begin
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if SPI_CLk'event and SPI_CLk ='1' then
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if N = 0 then
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OUT0 <= Vec0;
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OUT1 <= Vec1;
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OUT2 <= Vec2;
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OUT3 <= Vec3;
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OUT4 <= Vec4;
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OUT5 <= Vec5;
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OUT6 <= Vec6;
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OUT7 <= Vec7;
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end if;
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end if;
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end process;
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end ar_ADS1278_DRIVER;
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