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------------------------------------------------------------------------------
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-- This file is a part of the LPP VHDL IP LIBRARY
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-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-------------------------------------------------------------------------------
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-- Author : Alexis Jeandet
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-- Mail : alexis.jeandet@lpp.polytechnique.fr
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----------------------------------------------------------------------------
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library IEEE;
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use IEEE.numeric_std.all;
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use IEEE.std_logic_1164.all;
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entity saturation is
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generic (
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SIZE_INPUT : integer := 18;
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SIZE_OUTPUT : integer := 16);
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port (
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s_in : in std_logic_vector(SIZE_INPUT-1 downto 0);
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s_out : out std_logic_vector(SIZE_OUTPUT-1 downto 0)
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);
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end entity saturation;
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architecture beh of saturation is
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signal saturated : std_logic;
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constant all_one : std_logic_vector(SIZE_INPUT-1 downto SIZE_OUTPUT-1) := (others => '1');
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constant all_zero : std_logic_vector(SIZE_INPUT-1 downto SIZE_OUTPUT-1) := (others => '0');
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begin -- architecture beh
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SIZE_IN_inf_SIZE_OUT : if SIZE_INPUT < SIZE_OUTPUT generate
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s_out(SIZE_INPUT-1 downto 0) <= s_in(SIZE_INPUT-1 downto 0);
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all_inf_bits : for I in SIZE_OUTPUT-1 downto SIZE_INPUT generate
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s_out(I) <= s_in(SIZE_INPUT-1);
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end generate all_inf_bits;
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end generate SIZE_IN_inf_SIZE_OUT;
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SIZE_IN_equ_SIZE_OUT : if SIZE_INPUT = SIZE_OUTPUT generate
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s_out <= s_in;
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end generate SIZE_IN_equ_SIZE_OUT;
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SIZE_IN_sup_SIZE_OUT : if SIZE_INPUT > SIZE_OUTPUT generate
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saturated <= '0' when s_in(SIZE_INPUT-1 downto SIZE_OUTPUT-1) = all_zero else
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'0' when s_in(SIZE_INPUT-1 downto SIZE_OUTPUT-1) = all_one else
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'1';
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s_out(SIZE_OUTPUT-1) <= s_in(SIZE_INPUT-1);
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all_bits : for I in SIZE_OUTPUT-2 downto 0 generate
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s_out(I) <= s_in(I) when saturated = '0' else not s_in(SIZE_INPUT-1);
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end generate all_bits;
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end generate SIZE_IN_sup_SIZE_OUT;
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end architecture beh;
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