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------------------------------------------------------------------------------
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-- This file is a part of the LPP VHDL IP LIBRARY
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-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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------------------------------------------------------------------------------
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-- Author : Jean-christophe Pellion
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-- Mail : jean-christophe.pellion@lpp.polytechnique.fr
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------------------------------------------------------------------------------
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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ENTITY ramp_generator IS
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GENERIC (
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DATA_SIZE : INTEGER := 16;
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VALUE_UNSIGNED_INIT : INTEGER := 0;
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VALUE_UNSIGNED_INCR : INTEGER := 1;
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VALUE_UNSIGNED_MASK : INTEGER := 16#FFFF#);
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PORT (
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clk : IN STD_LOGIC;
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rstn : IN STD_LOGIC;
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new_data : IN STD_LOGIC;
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output_data : OUT STD_LOGIC_VECTOR(DATA_SIZE-1 DOWNTO 0));
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END ramp_generator;
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ARCHITECTURE beh OF ramp_generator IS
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SIGNAL data : STD_LOGIC_VECTOR(DATA_SIZE-1 DOWNTO 0);
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BEGIN -- beh
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PROCESS (clk, rstn)
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BEGIN -- PROCESS
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IF rstn = '0' THEN -- asynchronous reset (active low)
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data <= STD_LOGIC_VECTOR(to_unsigned(VALUE_UNSIGNED_INIT,DATA_SIZE))
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AND STD_LOGIC_VECTOR(to_unsigned(VALUE_UNSIGNED_MASK,DATA_SIZE));
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ELSIF clk'event AND clk = '1' THEN -- rising clock edge
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IF new_data = '1' THEN
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data <= STD_LOGIC_VECTOR(to_unsigned(VALUE_UNSIGNED_INCR + to_integer(UNSIGNED(data)),DATA_SIZE))
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AND STD_LOGIC_VECTOR(to_unsigned(VALUE_UNSIGNED_MASK ,DATA_SIZE));
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END IF;
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END IF;
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END PROCESS;
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output_data <= data;
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END beh;
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