HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib Files · lib/lpp/general_purpose/Clk_Divider2.vhd

Few fixes....

Few fixes. Whole LFR simulation WIP.

jeandet - - Load All Authors

File last commit:

r129:8459a437c1f1 alexis


                r682:c53e1b6b3045

default

Download file

             Clk_Divider2.vhd
        
                    36 lines
            
             | 685 B
            
                | text/x-vhdl
            
             |
                VhdlLexer
            
             / lib / lpp / general_purpose / Clk_Divider2.vhd
          
                    History
                
                 |
                  Annotation
                 | Raw
                 |Copy content
                 |Copy permalink

      -- ClkDivider.vhd

      library IEEE;

      use IEEE.std_logic_1164.all;

      use IEEE.numeric_std.all;

      entity Clk_Divider2 is 

      generic(N : integer := 16);

      port(

          clk_in  :   in  std_logic;

          clk_out :   out std_logic

      );

      end entity;

      architecture ar_ClkDivider of Clk_Divider2 is

      signal  cpt     :   integer range 0 to N/2-1;

      signal  clk_int :   std_logic:='0';

      begin

      clk_out <=  clk_int;

      process(clk_in)

      begin

          if clk_in'event and clk_in = '1' then

              if cpt = N/2-1 then

                  clk_int <= not clk_int;

                  cpt       <=  0;

              else

                  cpt       <=  cpt + 1;

              end if;

          end if;

      end process;

      end ar_ClkDivider;

	Site-wide shortcuts
/	Use quick search box
g h	Goto home page
g g	Goto my private gists page
g G	Goto my public gists page
g 0-9	Goto bookmarked items from 0-9
n r	New repository page
n g	New gist page

	Repositories
g s	Goto summary page
g c	Goto changelog page
g f	Goto files page
g F	Goto files page with file search activated
g p	Goto pull requests page
g o	Goto repository settings
g O	Goto repository access permissions settings
t s	Toggle sidebar on some pages

				-- ClkDivider.vhd
				library IEEE;
				use IEEE.std_logic_1164.all;
				use IEEE.numeric_std.all;



				entity Clk_Divider2 is
				generic(N : integer := 16);
				port(
				clk_in : in std_logic;
				clk_out : out std_logic
				);
				end entity;



				architecture ar_ClkDivider of Clk_Divider2 is
				signal cpt : integer range 0 to N/2-1;
				signal clk_int : std_logic:='0';
				begin

				clk_out <= clk_int;

				process(clk_in)
				begin
				if clk_in'event and clk_in = '1' then
				if cpt = N/2-1 then
				clk_int <= not clk_int;
				cpt <= 0;
				else
				cpt <= cpt + 1;
				end if;
				end if;
				end process;
				end ar_ClkDivider;