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------------------------------------------------------------------------------
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-- This file is a part of the LPP VHDL IP LIBRARY
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-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-------------------------------------------------------------------------------
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-- Author : Alexis Jeandet
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-- Mail : alexis.jeandet@lpp.polytechnique.fr
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----------------------------------------------------------------------------
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LIBRARY IEEE;
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USE IEEE.numeric_std.ALL;
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USE IEEE.std_logic_1164.ALL;
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LIBRARY lpp;
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USE lpp.general_purpose.ALL;
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--IDLE = 0000
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--MAC = 0001
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--MULT = 0010 and set MULT in ADD reg
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--ADD = 0011
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--CLRMAC = 0100
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ENTITY ALU_V0 IS
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GENERIC(
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Arith_en : INTEGER := 1;
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Logic_en : INTEGER := 1;
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Input_SZ_1 : INTEGER := 16;
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Input_SZ_2 : INTEGER := 9
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);
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PORT(
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clk : IN STD_LOGIC;
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reset : IN STD_LOGIC;
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ctrl : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
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OP1 : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0);
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OP2 : IN STD_LOGIC_VECTOR(Input_SZ_2-1 DOWNTO 0);
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RES : OUT STD_LOGIC_VECTOR(Input_SZ_1+Input_SZ_2-1 DOWNTO 0)
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);
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END ENTITY;
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ARCHITECTURE ar_ALU OF ALU_V0 IS
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SIGNAL clr_MAC : STD_LOGIC := '1';
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BEGIN
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clr_MAC <= '1' WHEN ctrl = "0100" OR ctrl = "0101" OR ctrl = "0110" ELSE '0';
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arith : IF Arith_en = 1 GENERATE
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MACinst : MAC_V0
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GENERIC MAP(Input_SZ_1, Input_SZ_2)
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PORT MAP(clk, reset, clr_MAC, ctrl(1 DOWNTO 0), OP1, OP2, RES);
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END GENERATE;
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END ARCHITECTURE;
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