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------------------------------------------------------------------------------
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-- This file is a part of the LPP VHDL IP LIBRARY
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-- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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------------------------------------------------------------------------------
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-- Author : Martin Morlot
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-- Mail : martin.morlot@lpp.polytechnique.fr
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------------------------------------------------------------------------------
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LIBRARY IEEE;
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USE IEEE.std_logic_1164.ALL;
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USE IEEE.numeric_std.ALL;
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ENTITY Linker_FFT IS
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GENERIC(
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Data_sz : INTEGER RANGE 1 TO 32 := 16;
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NbData : INTEGER RANGE 1 TO 512 := 256
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);
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PORT(
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clk : IN STD_LOGIC;
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rstn : IN STD_LOGIC;
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Ready : IN STD_LOGIC; --
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Valid : IN STD_LOGIC; --
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Full : IN STD_LOGIC_VECTOR(4 DOWNTO 0); --
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Data_re : IN STD_LOGIC_VECTOR(Data_sz-1 DOWNTO 0); --
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Data_im : IN STD_LOGIC_VECTOR(Data_sz-1 DOWNTO 0); --
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Read : OUT STD_LOGIC; -- Link_Read
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Write : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); --
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ReUse : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
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DATA : OUT STD_LOGIC_VECTOR((5*Data_sz)-1 DOWNTO 0)
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);
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END ENTITY;
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ARCHITECTURE ar_Linker OF Linker_FFT IS
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TYPE etat IS (eX, e0, e1, e2);
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SIGNAL ect : etat;
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SIGNAL DataTmp : STD_LOGIC_VECTOR(Data_sz-1 DOWNTO 0);
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SIGNAL sRead : STD_LOGIC;
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SIGNAL sReady : STD_LOGIC;
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SIGNAL FifoCpt : INTEGER RANGE 0 TO 4 := 0;
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BEGIN
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PROCESS(clk, rstn)
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BEGIN
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IF(rstn = '0')then
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ect <= e0;
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sRead <= '0';
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sReady <= '0';
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Write <= (OTHERS => '1');
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Reuse <= (OTHERS => '0');
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FifoCpt <= 0;
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ELSIF(clk'EVENT AND clk = '1')then
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sReady <= Ready;
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IF(sReady = '1' and Ready = '0')THEN
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IF(FifoCpt = 4)THEN
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FifoCpt <= 0;
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ELSE
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FifoCpt <= FifoCpt + 1;
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END IF;
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ELSIF(Ready = '1')then
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sRead <= NOT sRead;
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ELSE
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sRead <= '0';
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END IF;
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CASE ect IS
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WHEN e0 =>
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Write(FifoCpt) <= '1';
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IF(Valid = '1' and Full(FifoCpt) = '0')THEN
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DataTmp <= Data_im;
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DATA(((FifoCpt+1)*Data_sz)-1 DOWNTO (FifoCpt*Data_sz)) <= Data_re;
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Write(FifoCpt) <= '0';
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ect <= e1;
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ELSIF(Full(FifoCpt) = '1')then
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ReUse(FifoCpt) <= '1';
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END IF;
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WHEN e1 =>
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DATA(((FifoCpt+1)*Data_sz)-1 DOWNTO (FifoCpt*Data_sz)) <= DataTmp;
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ect <= e0;
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WHEN OTHERS =>
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NULL;
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END CASE;
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END IF;
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END PROCESS;
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Read <= sRead;
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END ARCHITECTURE;
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