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------------------------------------------------------------------------------
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-- This file is a part of the LPP VHDL IP LIBRARY
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-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-------------------------------------------------------------------------------
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-- Author : Jean-christophe PELLION
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-- Mail : jean-christophe.pellion@lpp.polytechnique.fr
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-------------------------------------------------------------------------------
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LIBRARY IEEE;
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USE IEEE.STD_LOGIC_1164.ALL;
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USE IEEE.std_logic_arith.ALL;
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LIBRARY lpp;
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use lpp.iir_filter.all;
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ENTITY Downsampling IS
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GENERIC (
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ChanelCount : INTEGER;
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SampleSize : INTEGER;
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DivideParam : INTEGER );
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PORT (
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clk : IN STD_LOGIC;
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rstn : IN STD_LOGIC;
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sample_in_val : IN STD_LOGIC;
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sample_in : IN samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0);
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sample_out_val : OUT STD_LOGIC;
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sample_out : OUT samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0)
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);
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END Downsampling;
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ARCHITECTURE beh OF Downsampling IS
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SIGNAL counter : INTEGER RANGE 0 TO DivideParam-1;
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BEGIN -- beh
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PROCESS (clk, rstn)
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BEGIN -- PROCESS
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IF rstn = '0' THEN -- asynchronous reset (active low)
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counter <= 0;
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sample_out_val <= '0';
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all_sampl: FOR I IN ChanelCount-1 DOWNTO 0 LOOP
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all_bit: FOR J IN SampleSize-1 DOWNTO 0 LOOP
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sample_out(I,J) <= '0';
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END LOOP all_bit;
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END LOOP all_sampl;
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ELSIF clk'event AND clk = '1' THEN -- rising clock edge
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IF sample_in_val = '1' THEN
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IF counter = 0 THEN
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counter <= DivideParam-1;
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sample_out_val <= '1';
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sample_out <= sample_in;
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ELSE
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counter <= counter-1;
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sample_out_val <= '0';
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END IF;
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ELSE
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sample_out_val <= '0';
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END IF;
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END IF;
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END PROCESS;
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END beh;
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