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------------------------------------------------------------------------------
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-- This file is a part of the LPP VHDL IP LIBRARY
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-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-------------------------------------------------------------------------------
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-- Author : Alexis Jeandet
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-- Mail : alexis.jeandet@lpp.polytechnique.fr
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-------------------------------------------------------------------------------
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library IEEE;
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use IEEE.numeric_std.all;
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use IEEE.std_logic_1164.all;
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library lpp;
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use lpp.iir_filter.all;
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use lpp.FILTERcfg.all;
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use lpp.general_purpose.all;
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--Maximum filter speed(smps/s) = Fclk/(Nchanels*Ncoefs)
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--exemple 26MHz sys clock and 6 chanels @ 110ksmps/s
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--Ncoefs = 26 000 000 /(6 * 110 000) = 39 coefs
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entity FILTER is
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generic(Smpl_SZ : integer := 16;
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ChanelsCNT : integer := 3
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);
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port(
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reset : in std_logic;
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clk : in std_logic;
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sample_clk : in std_logic;
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Sample_IN : in std_logic_vector(Smpl_SZ*ChanelsCNT-1 downto 0);
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Sample_OUT : out std_logic_vector(Smpl_SZ*ChanelsCNT-1 downto 0)
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);
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end entity;
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architecture ar_FILTER of FILTER is
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signal ALU_ctrl : std_logic_vector(3 downto 0);
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signal Sample : std_logic_vector(Smpl_SZ-1 downto 0);
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signal Coef : std_logic_vector(Coef_SZ-1 downto 0);
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signal ALU_OUT : std_logic_vector(Smpl_SZ+Coef_SZ-1 downto 0);
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begin
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--==============================================================
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--=========================A L U================================
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--==============================================================
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ALU1 : ALU
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generic map(
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Arith_en => 1,
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Logic_en => 0,
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Input_SZ_1 => Smpl_SZ,
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Input_SZ_2 => Coef_SZ
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)
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port map(
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clk => clk,
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reset => reset,
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ctrl => ALU_ctrl,
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OP1 => Sample,
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OP2 => Coef,
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RES => ALU_OUT
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);
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--==============================================================
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--==============================================================
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--===============F I L T E R C O N T R O L E R================
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--==============================================================
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filterctrlr1 : FilterCTRLR
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port map(
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reset => reset,
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clk => clk,
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sample_clk => sample_clk,
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ALU_Ctrl => ALU_ctrl,
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sample_in => sample_Tbl,
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coef => Coef,
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sample => Sample
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);
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--==============================================================
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chanelCut : for i in 0 to ChanelsCNT-1 generate
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sample_Tbl(i) <= Sample_IN((i+1)*Smpl_SZ-1 downto i*Smpl_SZ);
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end generate;
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end ar_FILTER;
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