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------------------------------------------------------------------------------
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-- This file is a part of the LPP VHDL IP LIBRARY
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-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-------------------------------------------------------------------------------
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-- Author : Alexis Jeandet
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-- Mail : alexis.jeandet@lpp.polytechnique.fr
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library grlib;
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use grlib.amba.all;
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use grlib.stdlib.all;
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use grlib.devices.all;
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library lpp;
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use lpp.iir_filter.all;
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use lpp.general_purpose.all;
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use lpp.lpp_amba.all;
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use lpp.apb_devices_list.all;
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entity APB_IIR_Filter is
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generic (
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tech : integer := 0;
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pindex : integer := 0;
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paddr : integer := 0;
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pmask : integer := 16#fff#;
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pirq : integer := 0;
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abits : integer := 8;
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Sample_SZ : integer := 16;
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ChanelsCount : integer := 1;
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Coef_SZ : integer := 9;
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CoefCntPerCel: integer := 6;
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Cels_count : integer := 5;
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virgPos : integer := 7;
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Mem_use : integer := use_RAM
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);
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port (
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rst : in std_logic;
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clk : in std_logic;
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apbi : in apb_slv_in_type;
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apbo : out apb_slv_out_type;
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-- sample_clk : in std_logic;
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sample_clk_out : out std_logic;
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GOtest : out std_logic;
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-- sample_in : in samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0);
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-- sample_out : out samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0);
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CoefsInitVal : in std_logic_vector((Cels_count*CoefCntPerCel*Coef_SZ)-1 downto 0) := (others => '1')
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);
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end entity;
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architecture AR_APB_IIR_Filter of APB_IIR_Filter is
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constant REVISION : integer := 1;
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constant pconfig : apb_config_type := (
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0 => ahb_device_reg (VENDOR_LPP, LPP_IIR_CEL_FILTER, 0, REVISION, 0),
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1 => apb_iobar(paddr, pmask));
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type FILTERreg is record
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Config : std_logic;
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SampleIN : samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0);
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SampleOUT : samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0);
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regin : in_IIR_CEL_reg;
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regout : out_IIR_CEL_reg;
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end record;
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signal Rdata : std_logic_vector(31 downto 0);
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signal r : FILTERreg;
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signal filter_reset : std_logic:='0';
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signal smp_cnt : integer :=0;
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signal sample_clk_out_R : std_logic;
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signal RawCoefs : std_logic_vector(((Coef_SZ*CoefCntPerCel*Cels_count)-1) downto 0);
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signal sample_clk : std_logic;
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--signal sample_in : samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0);
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--signal sample_out : samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0);
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type CoefCelT is array(0 to (CoefCntPerCel/2)-1) of std_logic_vector(Coef_SZ-1 downto 0);
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type CoefTblT is array(0 to Cels_count-1) of CoefCelT;
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type CoefsRegT is record
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numCoefs : CoefTblT;
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denCoefs : CoefTblT;
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end record;
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signal CoefsReg : CoefsRegT;
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signal CoefsReg_d : CoefsRegT;
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begin
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filter_reset <= rst and r.regin.config(0);
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sample_clk_out <= r.Config;
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filter : IIR_CEL_FILTER
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generic map(tech,Sample_SZ,ChanelsCount,Coef_SZ,CoefCntPerCel,Cels_count,Mem_use)
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port map(
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reset => filter_reset,
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clk => clk,
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sample_clk => r.Config,
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regs_in => r.regin,
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regs_out => r.regout,
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sample_in => r.SampleIN,
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sample_out => r.SampleOUT,
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GOtest => GOtest,
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coefs => RawCoefs
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);
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--process(rst,sample_clk)
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--begin
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--if rst = '0' then
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-- smp_cnt <= 0;
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-- sample_clk_out_R <= '0';
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--elsif r.Config'event and r.Config = '1' then
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-- if smp_cnt = 1 then
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-- smp_cnt <= 0;
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-- sample_clk_out_R <= not sample_clk_out_R;
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-- else
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-- smp_cnt <= smp_cnt +1;
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-- end if;
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--end if;
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--end process;
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coefsConnectL0: for z in 0 to Cels_count-1 generate
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coefsConnectL1: for y in 0 to (CoefCntPerCel/2)-1 generate
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RawCoefs(((((z*CoefCntPerCel+y)+1)*Coef_SZ)-1) downto (((z*CoefCntPerCel+y))*Coef_SZ) ) <= CoefsReg_d.numCoefs(z)(y)(Coef_SZ-1 downto 0);
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RawCoefs(((((z*CoefCntPerCel+y+(CoefCntPerCel/2))+1)*Coef_SZ)-1) downto ((z*CoefCntPerCel+y+(CoefCntPerCel/2))*Coef_SZ)) <= CoefsReg_d.denCoefs(z)(y)(Coef_SZ-1 downto 0);
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end generate;
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end generate;
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process(rst,clk)
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begin
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if rst = '0' then
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r.regin.virgPos <= std_logic_vector(to_unsigned(virgPos,5));
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coefsRstL0: for z in 0 to Cels_count-1 loop
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coefsRstL1: for y in 0 to (CoefCntPerCel/2)-1 loop
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CoefsReg.numCoefs(z)(y) <= CoefsInitVal(((((z*CoefCntPerCel+y)+1)*Coef_SZ)-1) downto (((z*CoefCntPerCel+y))*Coef_SZ) );
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CoefsReg.denCoefs(z)(y) <= CoefsInitVal(((((z*CoefCntPerCel+y+(CoefCntPerCel/2))+1)*Coef_SZ)-1) downto ((z*CoefCntPerCel+y+(CoefCntPerCel/2))*Coef_SZ));
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end loop;
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end loop;
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elsif clk'event and clk = '1' then
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CoefsReg_d <= CoefsReg;
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--APB Write OP
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if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
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case apbi.paddr(7 downto 2) is
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when "000000" =>
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r.Config <= apbi.pwdata(0);
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when "000001" =>
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r.SampleIN <= apbi.pwdata(17 downto 0);
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when "000011" =>
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r.regin.config(0) <= apbi.pwdata(0);
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when "000100" =>
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r.regin.virgPos <= apbi.pwdata(4 downto 0);
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when others =>
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for i in 0 to Cels_count-1 loop
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for j in 0 to (CoefCntPerCel/2) - 1 loop
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if apbi.paddr(9 downto 2) = std_logic_vector(TO_UNSIGNED((2+ (i*(CoefCntPerCel/2))+j),8)) then
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CoefsReg.numCoefs(i)(j) <= apbi.pwdata(Coef_SZ-1 downto 0);
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CoefsReg.denCoefs(i)(j) <= apbi.pwdata((Coef_SZ+15) downto 16);
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end if;
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end loop;
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end loop;
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end case;
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end if;
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--APB Read OP
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if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
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case apbi.paddr(7 downto 2)is
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when "000000" =>
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Rdata(31 downto 1) <= (others => '0');
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Rdata(0) <= r.Config;
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when "000001" =>
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Rdata(31 downto 18) <= (others => '0');
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Rdata(17 downto 0) <= r.SampleIN;
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when "000010" =>
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Rdata(31 downto 18) <= (others => '0');
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Rdata(17 downto 0) <= r.SampleOUT;
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when "000011" =>
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Rdata(7 downto 0) <= std_logic_vector(TO_UNSIGNED(ChanelsCount,8));
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Rdata(15 downto 8) <= std_logic_vector(TO_UNSIGNED(Sample_SZ,8));
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Rdata(23 downto 16) <= std_logic_vector(TO_UNSIGNED(CoefCntPerCel,8));
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Rdata(31 downto 24) <= std_logic_vector(TO_UNSIGNED(Cels_count,8));
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when "000100" =>
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Rdata(4 downto 0) <= r.regin.virgPos;
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Rdata(15 downto 8) <= std_logic_vector(TO_UNSIGNED(Coef_SZ,8));
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Rdata(7 downto 5) <= (others => '0');
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Rdata(31 downto 16) <= (others => '0');
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when others =>
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for i in 0 to Cels_count-1 loop
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for j in 0 to (CoefCntPerCel/2) - 1 loop
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if apbi.paddr(9 downto 2) = std_logic_vector(TO_UNSIGNED((2+ (i*(CoefCntPerCel/2))+j),8)) then
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Rdata(Coef_SZ-1 downto 0) <= CoefsReg_d.numCoefs(i)(j);
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Rdata((Coef_SZ+15) downto 16) <= CoefsReg_d.denCoefs(i)(j);
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end if;
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end loop;
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end loop;
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end case;
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end if;
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end if;
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apbo.pconfig <= pconfig;
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end process;
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apbo.prdata <= Rdata when apbi.penable = '1' ;
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end architecture;
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