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------------------------------------------------------------------------------
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-- This file is a part of the LPP VHDL IP LIBRARY
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-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-------------------------------------------------------------------------------
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-- Author : Jean-christophe Pellion
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-- Mail : jean-christophe.pellion@lpp.polytechnique.fr
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-- jean-christophe.pellion@easii-ic.com
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----------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE ieee.numeric_std.all;
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LIBRARY lpp;
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USE lpp.cic_pkg.ALL;
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USE lpp.data_type_pkg.ALL;
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ENTITY cic_lfr_add_sub IS
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PORT (
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clk : IN STD_LOGIC;
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rstn : IN STD_LOGIC;
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run : IN STD_LOGIC;
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OP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
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-- 00 A + B
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-- 01 A - B
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-- 10 A + B + Carry
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-- 11 A - B - Carry
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data_in_A : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
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data_in_B : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
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data_in_Carry : IN STD_LOGIC;
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data_out : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
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data_out_Carry : OUT STD_LOGIC
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);
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END cic_lfr_add_sub;
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ARCHITECTURE beh OF cic_lfr_add_sub IS
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SIGNAL data_carry : STD_LOGIC;
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SIGNAL STD_LOGIC_VECTOR_ZERO : STD_LOGIC_VECTOR(15 DOWNTO 0);
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SIGNAL data_add : STD_LOGIC_VECTOR(16 DOWNTO 0);
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SIGNAL data_sub : STD_LOGIC_VECTOR(16 DOWNTO 0);
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SIGNAL data : STD_LOGIC_VECTOR(16 DOWNTO 0);
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BEGIN
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STD_LOGIC_VECTOR_ZERO <= (OTHERS => '0');
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data_carry <= '0' WHEN OP(1) = '0' ELSE data_in_Carry;
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data_add <= STD_LOGIC_VECTOR( SIGNED('0' & data_in_A)
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+ SIGNED('0' & data_in_B)
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+ SIGNED(STD_LOGIC_VECTOR_ZERO & data_carry));
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data_sub <= STD_LOGIC_VECTOR( SIGNED('0' & data_in_A)
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- SIGNED('0' & data_in_B)
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- SIGNED(STD_LOGIC_VECTOR_ZERO & data_carry));
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data <= data_add WHEN OP(0) = '0' ELSE data_sub;
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PROCESS (clk, rstn)
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BEGIN -- PROCESS
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IF rstn = '0' THEN
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data_out_Carry <= '0';
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data_out <= (OTHERS => '0');
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ELSIF clk'event AND clk = '1' THEN
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IF run = '0' THEN
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data_out_Carry <= '0';
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data_out <= (OTHERS => '0');
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ELSE
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data_out_Carry <= data(16);
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data_out <= data(15 DOWNTO 0);
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END IF;
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END IF;
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END PROCESS;
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END beh;
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