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------------------------------------------------------------------------------
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-- This file is a part of the LPP VHDL IP LIBRARY
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-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-------------------------------------------------------------------------------
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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entity Clock_Serie is
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generic(N :integer := 695);
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port(
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clk, raz : in std_logic ;
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clock : out std_logic);
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end Clock_Serie;
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architecture ar_Clock_Serie of Clock_Serie is
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signal clockint : std_logic;
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signal countint : integer range 0 to N/2-1;
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begin
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process (clk,raz)
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begin
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if(raz = '0') then
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countint <= 0;
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clockint <= '0';
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elsif (clk' event and clk='1') then
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if (countint = N/2-1) then
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countint <= 0;
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clockint <= not clockint;
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else
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countint <= countint+1;
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end if;
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end if;
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end process;
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clock <= clockint;
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end ar_Clock_Serie;
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