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------------------------------------------------------------------------------
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-- This file is a part of the GRLIB VHDL IP LIBRARY
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-- Copyright (C) 2003 - 2008, Gaisler Research
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-- Copyright (C) 2008 - 2010, Aeroflex Gaisler
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-----------------------------------------------------------------------------
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-- Package: sim
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-- File: sim.vhd
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-- Author: Edvin Catovic - Gaisler Research
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-- Description: JTAG debug link communication test
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------------------------------------------------------------------------------
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-- pragma translate_off
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library ieee;
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use ieee.std_logic_1164.all;
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use std.textio.all;
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library grlib;
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use grlib.stdlib.all;
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use grlib.stdio.all;
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use grlib.amba.all;
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package jtagtst is
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procedure clkj(tmsi, tdii : in std_ulogic; tdoo : out std_ulogic;
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signal tck, tms, tdi : out std_ulogic;
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signal tdo : in std_ulogic;
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cp : in integer);
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procedure shift(dr : in boolean; len : in integer;
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din : in std_logic_vector; dout : out std_logic_vector;
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signal tck, tms, tdi : out std_ulogic;
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signal tdo : in std_ulogic;
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cp : in integer);
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procedure jtagcom(signal tdo : in std_ulogic;
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signal tck, tms, tdi : out std_ulogic;
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cp, start, addr : in integer;
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-- cp - TCK clock period in ns
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-- start - time in us when JTAG test
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-- is started
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-- addr - read/write operation destination address
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haltcpu : in boolean;
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justinit : in boolean := false; -- Only perform initialization
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reread : in boolean := false; -- Re-read on slow AHB response
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assertions : in boolean := false -- Allow output from assertions
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);
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subtype jword_type is std_logic_vector(31 downto 0);
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type jdata_vector_type is array (integer range <>) of jword_type;
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procedure jwritem(addr : in std_logic_vector;
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data : in jdata_vector_type;
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signal tck, tms, tdi : out std_ulogic;
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signal tdo : in std_ulogic;
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cp : in integer);
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procedure jreadm(addr : in std_logic_vector;
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data : out jdata_vector_type;
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signal tck, tms, tdi : out std_ulogic;
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signal tdo : in std_ulogic;
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cp : in integer;
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reread : in boolean := false;
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assertions : in boolean := false);
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procedure jwrite(addr, data : in std_logic_vector;
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signal tck, tms, tdi : out std_ulogic;
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signal tdo : in std_ulogic;
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cp : in integer);
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procedure jread(addr : in std_logic_vector;
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data : out std_logic_vector;
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signal tck, tms, tdi : out std_ulogic;
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signal tdo : in std_ulogic;
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cp : in integer;
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reread : in boolean := false;
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assertions : in boolean := false);
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procedure bscantest(signal tdo : in std_ulogic;
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signal tck, tms, tdi : out std_ulogic;
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cp: in integer);
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procedure bscansampre(signal tdo : in std_ulogic;
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signal tck, tms, tdi : out std_ulogic;
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nsigs: in integer;
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sigpre: in std_logic_vector; sigsamp: out std_logic_vector;
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cp: in integer);
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end;
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package body jtagtst is
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procedure clkj(tmsi, tdii : in std_ulogic; tdoo : out std_ulogic;
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signal tck, tms, tdi : out std_ulogic;
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signal tdo : in std_ulogic;
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cp : in integer) is
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begin
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tdi <= tdii;
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tck <= '0'; tms <= tmsi;
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wait for 2 * cp * 1 ns;
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tck <= '1'; tdoo := tdo;
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wait for 2 * cp * 1 ns;
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end;
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procedure shift(dr : in boolean; len : in integer;
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din : in std_logic_vector; dout : out std_logic_vector;
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signal tck, tms, tdi : out std_ulogic;
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signal tdo : in std_ulogic;
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cp : in integer) is
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variable dc : std_ulogic;
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begin
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clkj('0', '0', dc, tck, tms, tdi, tdo, cp);
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clkj('1', '0', dc, tck, tms, tdi, tdo, cp);
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if (not dr) then clkj('1', '0', dc, tck, tms, tdi, tdo, cp); end if;
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clkj('0', '0', dc, tck, tms, tdi, tdo, cp); -- capture
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clkj('0', '0', dc, tck, tms, tdi, tdo, cp); -- shift (state)
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for i in 0 to len-2 loop
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clkj('0', din(i), dout(i), tck, tms, tdi, tdo, cp);
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end loop;
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clkj('1', din(len-1), dout(len-1), tck, tms, tdi, tdo, cp); -- end shift, goto exit1
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clkj('1', '0', dc, tck, tms, tdi, tdo, cp); -- update ir/dr
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clkj('0', '0', dc, tck, tms, tdi, tdo, cp); -- run_test/idle
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end;
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procedure jwrite(addr, data : in std_logic_vector;
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signal tck, tms, tdi : out std_ulogic;
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signal tdo : in std_ulogic;
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cp : in integer) is
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variable tmp : std_logic_vector(32 downto 0);
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variable tmp2 : std_logic_vector(34 downto 0);
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variable dr : std_logic_vector(32 downto 0);
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variable dr2 : std_logic_vector(34 downto 0);
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variable hsize : std_logic_vector(1 downto 0);
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begin
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hsize := "10";
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wait for 10 * cp * 1 ns;
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shift(false, 6, B"010000", dr, tck, tms, tdi, tdo, cp); -- inst = addrreg
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wait for 5 * cp * 1 ns;
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tmp2 := '1' & hsize & addr;
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shift(true, 35, tmp2, dr2, tck, tms, tdi, tdo, cp); -- write add reg
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wait for 5 * cp * 1 ns;
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shift(false, 6, B"110000", dr, tck, tms, tdi, tdo, cp); -- inst = datareg
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wait for 5 * cp * 1 ns;
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tmp := '0' & data;
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shift(true, 33, tmp, dr, tck, tms, tdi, tdo, cp); -- write data reg
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end;
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procedure jread(addr : in std_logic_vector;
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data : out std_logic_vector;
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signal tck, tms, tdi : out std_ulogic;
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signal tdo : in std_ulogic;
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cp : in integer;
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reread : in boolean := false;
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assertions : in boolean := false) is
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variable tmp : std_logic_vector(32 downto 0);
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variable tmp2 : std_logic_vector(34 downto 0);
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variable dr : std_logic_vector(32 downto 0);
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variable dr2 : std_logic_vector(34 downto 0);
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variable hsize : std_logic_vector(1 downto 0);
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begin
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hsize := "10";
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wait for 10 * cp * 1 ns;
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shift(false, 6, B"010000", dr, tck, tms, tdi, tdo, cp); -- inst = addrreg
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wait for 5 * cp * 1 ns;
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tmp2 := '0' & hsize & addr;
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shift(true, 35, tmp2, dr2, tck, tms, tdi, tdo, cp); -- write add reg
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wait for 5 * cp * 1 ns;
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shift(false, 6, B"110000", dr, tck, tms, tdi, tdo, cp); -- inst = datareg
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wait for 5 * cp * 1 ns;
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tmp := (others => '0'); --tmp(32) := '1';
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shift(true, 33, tmp, dr, tck, tms, tdi, tdo, cp); -- read data reg
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assert dr(32) = '1' or not assertions
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report "JTAG READ: data read out before AHB access completed"
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severity warning;
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while dr(32) /= '1' and reread loop
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assert not assertions report "Re-reading JTAG data register" severity note;
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tmp := (others => '0');
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shift(true, 33, tmp, dr, tck, tms, tdi, tdo, cp); -- read data reg
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end loop;
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data := dr(31 downto 0);
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end;
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procedure jwritem(addr : in std_logic_vector;
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data : in jdata_vector_type;
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signal tck, tms, tdi : out std_ulogic;
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signal tdo : in std_ulogic;
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cp : in integer) is
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variable tmp : std_logic_vector(32 downto 0);
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variable tmp2 : std_logic_vector(34 downto 0);
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variable dr : std_logic_vector(32 downto 0);
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variable dr2 : std_logic_vector(34 downto 0);
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variable hsize : std_logic_vector(1 downto 0);
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begin
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hsize := "10";
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wait for 10 * cp * 1 ns;
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shift(false, 6, B"010000", dr, tck, tms, tdi, tdo, cp); -- inst = addrreg
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wait for 5 * cp * 1 ns;
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tmp2 := '1' & hsize & addr;
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shift(true, 35, tmp2, dr2, tck, tms, tdi, tdo, cp); -- write add reg
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wait for 5 * cp * 1 ns;
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shift(false, 6, B"110000", dr, tck, tms, tdi, tdo, cp); -- inst = datareg
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wait for 5 * cp * 1 ns;
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for i in data'left to data'right-1 loop
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tmp := '1' & data(i);
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shift(true, 33, tmp, dr, tck, tms, tdi, tdo, cp); -- write data reg
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end loop;
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tmp := '0' & data(data'right);
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shift(true, 33, tmp, dr, tck, tms, tdi, tdo, cp); -- write data reg
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end;
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procedure jreadm(addr : in std_logic_vector;
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data : out jdata_vector_type;
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signal tck, tms, tdi : out std_ulogic;
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signal tdo : in std_ulogic;
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cp : in integer;
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reread : in boolean := false;
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assertions : in boolean := false) is
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variable tmp : std_logic_vector(32 downto 0);
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variable tmp2 : std_logic_vector(34 downto 0);
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variable dr : std_logic_vector(32 downto 0);
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variable dr2 : std_logic_vector(34 downto 0);
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variable hsize : std_logic_vector(1 downto 0);
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begin
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hsize := "10";
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wait for 10 * cp * 1 ns;
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shift(false, 6, B"010000", dr, tck, tms, tdi, tdo, cp); -- inst = addrreg
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wait for 5 * cp * 1 ns;
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tmp2 := '0' & hsize & addr;
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shift(true, 35, tmp2, dr2, tck, tms, tdi, tdo, cp); -- write add reg
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wait for 5 * cp * 1 ns;
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shift(false, 6, B"110000", dr, tck, tms, tdi, tdo, cp); -- inst = datareg
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wait for 5 * cp * 1 ns;
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for i in data'left to data'right-1 loop
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tmp := (others => '0'); tmp(32) := '1';
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shift(true, 33, tmp, dr, tck, tms, tdi, tdo, cp); -- read data reg
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assert dr(32) = '1' or not assertions
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report "JTAG READ: data read out before AHB access completed"
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severity warning;
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while dr(32) /= '1' and reread loop
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assert not assertions report "Re-reading JTAG data register" severity note;
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tmp := (others => '0'); tmp(32) := '1';
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shift(true, 33, tmp, dr, tck, tms, tdi, tdo, cp); -- read data reg
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end loop;
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data(i) := dr(31 downto 0);
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end loop;
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tmp := (others => '0');
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shift(true, 33, tmp, dr, tck, tms, tdi, tdo, cp); -- read data reg
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assert dr(32) = '1' or not assertions
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report "JTAG READ: data read out before AHB access completed"
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severity warning;
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while dr(32) /= '1' and reread loop
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assert not assertions report "Re-reading JTAG data register" severity note;
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tmp := (others => '0');
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shift(true, 33, tmp, dr, tck, tms, tdi, tdo, cp); -- read data reg
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end loop;
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data(data'right) := dr(31 downto 0);
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end;
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procedure jtagcom(signal tdo : in std_ulogic;
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signal tck, tms, tdi : out std_ulogic;
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cp, start, addr : in integer;
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haltcpu : in boolean;
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justinit : in boolean := false;
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reread : in boolean := false;
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assertions : in boolean := false) is
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variable dc : std_ulogic;
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variable dr : std_logic_vector(32 downto 0);
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variable tmp : std_logic_vector(32 downto 0);
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variable data : std_logic_vector(31 downto 0);
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variable datav : jdata_vector_type(0 to 3);
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begin
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tck <= '0'; tms <= '0'; tdi <= '0';
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wait for start * 1 us;
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print("AHB JTAG TEST");
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for i in 1 to 5 loop -- reset
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clkj('1', '0', dc, tck, tms, tdi, tdo, cp);
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end loop;
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clkj('0', '0', dc, tck, tms, tdi, tdo, cp);
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--read IDCODE
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wait for 10 * cp * 1 ns;
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shift(true, 32, conv_std_logic_vector(0, 32), dr, tck, tms, tdi, tdo, cp);
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print("JTAG TAP ID:" & tost(dr(31 downto 0)));
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wait for 10 * cp * 1 ns;
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shift(false, 6, conv_std_logic_vector(63, 6), dr, tck, tms, tdi, tdo, cp); -- BYPASS
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--shift data through BYPASS reg
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shift(true, 32, conv_std_logic_vector(16#AAAA#, 16) & conv_std_logic_vector(16#AAAA#, 16), dr,
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tck, tms, tdi, tdo, cp);
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-- put CPUs in debug mode
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if haltcpu then
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jwrite(X"90000000", X"00000004", tck, tms, tdi, tdo, cp);
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jwrite(X"90000020", X"0000FFFF", tck, tms, tdi, tdo, cp);
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print("JTAG: Putting CPU in debug mode");
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end if;
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if false then
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jwrite(X"90000000", X"FFFFFFFF", tck, tms, tdi, tdo, cp);
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jread (X"90000000", data, tck, tms, tdi, tdo, cp, reread, assertions);
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print("JTAG WRITE " & tost(X"90000000") & ":" & tost(X"FFFFFFFF"));
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print("JTAG READ " & tost(X"90000000") & ":" & tost(data));
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jwrite(X"90100034", X"ABCD1234", tck, tms, tdi, tdo, cp);
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jread (X"90100034", data, tck, tms, tdi, tdo, cp, reread, assertions);
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print("JTAG WRITE " & tost(X"90100034") & ":" & tost(X"ABCD1234"));
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print("JTAG READ " & tost(X"90100034") & ":" & tost(data));
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jwrite(X"90200058", X"ABCDEF01", tck, tms, tdi, tdo, cp);
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jread (X"90200058", data, tck, tms, tdi, tdo, cp, reread, assertions);
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print("JTAG WRITE " & tost(X"90200058") & ":" & tost(X"ABCDEF01"));
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print("JTAG READ " & tost(X"90200058") & ":" & tost(data));
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jwrite(X"90300000", X"ABCD1234", tck, tms, tdi, tdo, cp);
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jread (X"90300000", data, tck, tms, tdi, tdo, cp, reread, assertions);
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print("JTAG WRITE " & tost(X"90300000") & ":" & tost(X"ABCD1234"));
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print("JTAG READ " & tost(X"90300000") & ":" & tost(data));
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jwrite(X"90400000", X"ABCD1234", tck, tms, tdi, tdo, cp);
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jread (X"90400000", data, tck, tms, tdi, tdo, cp, reread, assertions);
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print("JTAG WRITE " & tost(X"90400000") & ":" & tost(X"ABCD1234"));
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print("JTAG READ " & tost(X"90400000") & ":" & tost(data));
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jwrite(X"90400024", X"0000000C", tck, tms, tdi, tdo, cp);
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jwrite(X"90700100", X"ABCD1234", tck, tms, tdi, tdo, cp);
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jread (X"90700100", data, tck, tms, tdi, tdo, cp, reread, assertions);
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print("JTAG WRITE ITAG :" & tost(X"00000100") & ":" & tost(X"ABCD1234"));
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print("JTAG READ ITAG :" & tost(X"00000100") & ":" & tost(data));
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jwrite(X"90400024", X"0000000D", tck, tms, tdi, tdo, cp);
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jwrite(X"90700100", X"ABCD1234", tck, tms, tdi, tdo, cp);
|
|
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jread (X"90700100", data, tck, tms, tdi, tdo, cp, reread, assertions);
|
|
|
print("JTAG WRITE IDATA:" & tost(X"00000100") & ":" & tost(X"ABCD1234"));
|
|
|
print("JTAG READ IDATA:" & tost(X"00000100") & ":" & tost(data));
|
|
|
|
|
|
jwrite(X"90400024", X"0000000E", tck, tms, tdi, tdo, cp);
|
|
|
jwrite(X"90700100", X"ABCD1234", tck, tms, tdi, tdo, cp);
|
|
|
jread (X"90700100", data, tck, tms, tdi, tdo, cp, reread, assertions);
|
|
|
print("JTAG WRITE DTAG :" & tost(X"00000100") & ":" & tost(X"ABCD1234"));
|
|
|
print("JTAG READ DTAG :" & tost(X"00000100") & ":" & tost(data));
|
|
|
|
|
|
jwrite(X"90400024", X"0000000F", tck, tms, tdi, tdo, cp);
|
|
|
jwrite(X"90700100", X"ABCD1234", tck, tms, tdi, tdo, cp);
|
|
|
jread (X"90700100", data, tck, tms, tdi, tdo, cp, reread, assertions);
|
|
|
print("JTAG WRITE DDATA:" & tost(X"00000100") & ":" & tost(X"ABCD1234"));
|
|
|
print("JTAG READ DDATA:" & tost(X"00000100") & ":" & tost(data));
|
|
|
end if;
|
|
|
|
|
|
if not justinit then
|
|
|
|
|
|
--jwritem(addr, (X"00000010", X"00000010", X"00000010", X"00000010"), tck, tms, tdi, tdo, cp);
|
|
|
datav(0) := X"00000010"; datav(1) := X"00000011"; datav(2) := X"00000012"; datav(3) := X"00000013";
|
|
|
jwritem(conv_std_logic_vector(addr, 32), datav, tck, tms, tdi, tdo, cp);
|
|
|
print("JTAG WRITE " & tost(conv_std_logic_vector(addr,32)) & ":" & tost(X"00000010") & " " & tost(X"00000011") & " " & tost(X"00000012") & " " & tost(X"00000013"));
|
|
|
|
|
|
datav := (others => (others => '0'));
|
|
|
jreadm(conv_std_logic_vector(addr, 32), datav, tck, tms, tdi, tdo, cp, reread, assertions);
|
|
|
print("JTAG READ " & tost(conv_std_logic_vector(addr,32)) & ":" & tost(datav(0)) & " " & tost(datav(1)) & " " & tost(datav(2)) & " " & tost(datav(3)));
|
|
|
|
|
|
-- Not affected by 'assertions' parameter
|
|
|
assert (datav(0) = X"00000010") and (datav(1) = X"00000011") and (datav(2) = X"00000012") and (datav(3) = X"00000013")
|
|
|
report "JTAG test failed" severity failure;
|
|
|
|
|
|
print("JTAG test passed");
|
|
|
|
|
|
end if;
|
|
|
|
|
|
end procedure;
|
|
|
|
|
|
-- Sample/Preload
|
|
|
procedure bscansampre(signal tdo : in std_ulogic;
|
|
|
signal tck, tms, tdi : out std_ulogic;
|
|
|
nsigs: in integer;
|
|
|
sigpre: in std_logic_vector; sigsamp: out std_logic_vector;
|
|
|
cp: in integer) is
|
|
|
variable tmp: std_logic_vector(5 downto 0);
|
|
|
begin
|
|
|
shift(false,6, conv_std_logic_vector(5,6), tmp, tck,tms,tdi,tdo, cp);
|
|
|
shift(true, nsigs, sigpre, sigsamp, tck,tms,tdi,tdo, cp);
|
|
|
end procedure;
|
|
|
|
|
|
-- Boundary scan test
|
|
|
procedure bscantest(signal tdo : in std_ulogic;
|
|
|
signal tck, tms, tdi : out std_ulogic;
|
|
|
cp: in integer) is
|
|
|
variable tmpin,tmpout: std_logic_vector(1499 downto 0);
|
|
|
variable i,bslen: integer;
|
|
|
variable dc: std_logic;
|
|
|
variable tmp6: std_logic_vector(5 downto 0);
|
|
|
variable tmp1: std_logic_vector(0 downto 0);
|
|
|
begin
|
|
|
print("[bscan] Boundary scan test starting...");
|
|
|
for i in 1 to 5 loop -- reset
|
|
|
clkj('1', '0', dc, tck, tms, tdi, tdo, cp);
|
|
|
end loop;
|
|
|
clkj('0', '0', dc, tck, tms, tdi, tdo, cp);
|
|
|
-- Probe length of boundary scan chain
|
|
|
tmpin := (others => '0');
|
|
|
tmpin(tmpin'length/2) := '1';
|
|
|
bscansampre(tdo,tck,tms,tdi,tmpin'length,tmpin,tmpout,cp);
|
|
|
i := tmpout'length/2;
|
|
|
for x in tmpout'length/2 to tmpout'high loop
|
|
|
if tmpout(x)='1' then
|
|
|
-- print("tmpout(" & tost(x) & ") set");
|
|
|
i := x;
|
|
|
end if;
|
|
|
end loop;
|
|
|
bslen := i-tmpout'length/2;
|
|
|
print("[bscan] Detected boundary scan chain length: " & tost(bslen));
|
|
|
print("[bscan] Looping over outputs...");
|
|
|
shift(false,6, conv_std_logic_vector(6,6), tmp6, tck,tms,tdi,tdo, cp); -- extest
|
|
|
for x in 0 to bslen loop
|
|
|
tmpin :=(others => '0');
|
|
|
tmpin(x) := '1';
|
|
|
shift(true, bslen, tmpin(bslen-1 downto 0), tmpout(bslen-1 downto 0), tck,tms,tdi,tdo, cp);
|
|
|
end loop;
|
|
|
print("[bscan] Looping over inputs...");
|
|
|
shift(false,6, conv_std_logic_vector(7,6), tmp6, tck,tms,tdi,tdo, cp); -- intest
|
|
|
for x in 0 to bslen loop
|
|
|
tmpin :=(others => '0');
|
|
|
tmpin(x) := '1';
|
|
|
shift(true, bslen, tmpin(bslen-1 downto 0), tmpout(bslen-1 downto 0), tck,tms,tdi,tdo, cp);
|
|
|
end loop;
|
|
|
end procedure;
|
|
|
|
|
|
end;
|
|
|
|
|
|
-- pragma translate_on
|
|
|
|
|
|
|