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-- tb_TOP_Serial_Driver_Wcounter.vhd
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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entity tb_TOP_Serial_Driver_Wcounter is
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end entity;
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architecture ar_tb_TOP_Serial_Driver_Wcounter of tb_TOP_Serial_Driver_Wcounter is
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constant Speed : integer := 4*1000*1000;
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constant Tclk : time := real(1000*1000*1000/Speed) * 1 ns;
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constant Size : integer := 8;
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constant MinFCnt: integer := 144;
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constant MajFCnt: integer := 64;
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signal clk : std_logic := '0';
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signal sclk : std_logic := '0';
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signal Gate : std_logic:='1';
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signal Data : std_logic;
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signal MinF : std_logic:='1';
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signal MajF : std_logic:='1';
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signal flag : std_logic;
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begin
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SD0 : entity work.TOP_Serial_Driver_Wcounter
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--generic map(Size,MinFCnt)
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generic map(Size,MinFCnt,MajFCnt)
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port map(clk,sclk,Gate,MinF,MajF,Data);
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sclk <= not sclk after Tclk/2;
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clk <= not clk after 20ns;
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process
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begin
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gate <= '1';
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wait for (48)*Tclk;
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gate <= '0'; --1 ADMLF1.1
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wait for (16)*Tclk;
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gate <= '1';
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wait for (48)*Tclk;
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gate <= '0'; --2 ADMLF2.1
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wait for (32)*Tclk;
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gate <= '1';
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wait for (16)*Tclk;
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gate <= '0'; --3 ADMDC1 LSB
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wait for (48)*Tclk;
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gate <= '1';
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wait for (16)*Tclk;
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gate <= '0'; --4 ADMDC2 LSB
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wait for (32)*Tclk;
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gate <= '1';
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wait for (48)*Tclk;
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gate <= '0';
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wait for (16)*Tclk;
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gate <= '1';
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wait for (48)*Tclk;
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gate <= '0';
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wait for (16)*Tclk;
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gate <= '1';
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wait for (48)*Tclk;
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gate <= '0';
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wait for (16)*Tclk;
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gate <= '1';
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wait for (48)*Tclk;
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gate <= '0';
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wait for (16)*Tclk;
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gate <= '1';
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wait for (48)*Tclk;
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gate <= '0';
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wait for (16)*Tclk;
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gate <= '1';
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wait for (48)*Tclk;
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gate <= '0';
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wait for (16)*Tclk;
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gate <= '1';
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wait for (48)*Tclk;
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gate <= '0';
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wait for (16)*Tclk;
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gate <= '1';
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wait for (48)*Tclk;
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gate <= '0';
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wait for (16)*Tclk;
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gate <= '1';
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wait for (48)*Tclk;
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gate <= '0';
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wait for (16)*Tclk;
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gate <= '1';
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wait for (48)*Tclk;
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gate <= '0';
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wait for (16)*Tclk;
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gate <= '1';
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wait for (48)*Tclk;
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gate <= '0';
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wait for (16)*Tclk;
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gate <= '1';
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wait for (48)*Tclk;
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gate <= '0';
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wait for (16)*Tclk;
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gate <= '1';
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wait for (48)*Tclk;
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gate <= '0';
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wait for (16)*Tclk;
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gate <= '1';
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wait for (48)*Tclk;
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gate <= '0';
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wait for (16)*Tclk;
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gate <= '1';
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end process;
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process
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begin
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MinF <= '0';
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wait for Tclk;
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MinF <= '1';
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wait for (MinFCnt)*(Size)*Tclk-Tclk;
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end process;
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process
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begin
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MajF <= '0';
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wait for Tclk;
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MajF <= '1';
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wait for (MajFCnt)*(MinFCnt)*(Size)*Tclk-Tclk;
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end process;
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end ar_tb_TOP_Serial_Driver_Wcounter;
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