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------------------------------------------------------------------------------
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-- This file is a part of the LPP VHDL IP LIBRARY
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-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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------------------------------------------------------------------------------
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-- Author : Martin Morlot
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-- Mail : martin.morlot@lpp.polytechnique.fr
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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library grlib;
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use grlib.amba.all;
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use std.textio.all;
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library lpp;
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use lpp.lpp_amba.all;
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library gaisler;
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use gaisler.misc.all;
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use gaisler.memctrl.all;
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library techmap;
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use techmap.gencomp.all;
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--! Package contenant tous les programmes qui forment le composant int�gr� dans le l�on
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package lpp_memory is
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component APB_FIFO is
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generic (
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tech : integer := apa3;
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pindex : integer := 0;
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paddr : integer := 0;
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pmask : integer := 16#fff#;
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pirq : integer := 0;
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abits : integer := 8;
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FifoCnt : integer := 2;
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Data_sz : integer := 16;
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Addr_sz : integer := 9;
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Enable_ReUse : std_logic := '0';
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Mem_use : integer := use_RAM;
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R : integer := 1;
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W : integer := 1
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);
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port (
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clk : in std_logic; --! Horloge du composant
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rst : in std_logic; --! Reset general du composant
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rclk : in std_logic;
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wclk : in std_logic;
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ReUse : in std_logic_vector(FifoCnt-1 downto 0);
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REN : in std_logic_vector(FifoCnt-1 downto 0); --! Instruction de lecture en m�moire
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WEN : in std_logic_vector(FifoCnt-1 downto 0); --! Instruction d'�criture en m�moire
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Empty : out std_logic_vector(FifoCnt-1 downto 0); --! Flag, M�moire vide
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Full : out std_logic_vector(FifoCnt-1 downto 0); --! Flag, M�moire pleine
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RDATA : out std_logic_vector((FifoCnt*Data_sz)-1 downto 0); --! Registre de donn�es en entr�e
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WDATA : in std_logic_vector((FifoCnt*Data_sz)-1 downto 0); --! Registre de donn�es en sortie
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WADDR : out std_logic_vector((FifoCnt*Addr_sz)-1 downto 0); --! Registre d'addresse (�criture)
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RADDR : out std_logic_vector((FifoCnt*Addr_sz)-1 downto 0); --! Registre d'addresse (lecture)
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apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus
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apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
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);
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end component;
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component lpp_fifo is
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generic(
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tech : integer := 0;
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Mem_use : integer := use_RAM;
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Enable_ReUse : std_logic := '0';
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DataSz : integer range 1 to 32 := 8;
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abits : integer range 2 to 12 := 8
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);
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port(
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rstn : in std_logic;
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ReUse : in std_logic; --27/01/12
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rclk : in std_logic;
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ren : in std_logic;
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rdata : out std_logic_vector(DataSz-1 downto 0);
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empty : out std_logic;
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raddr : out std_logic_vector(abits-1 downto 0);
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wclk : in std_logic;
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wen : in std_logic;
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wdata : in std_logic_vector(DataSz-1 downto 0);
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full : out std_logic;
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waddr : out std_logic_vector(abits-1 downto 0)
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);
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end component;
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component lppFIFOxN is
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generic(
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tech : integer := 0;
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Mem_use : integer := use_RAM;
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Data_sz : integer range 1 to 32 := 8;
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Addr_sz : integer range 1 to 32 := 8;
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FifoCnt : integer := 1;
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Enable_ReUse : std_logic := '0'
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);
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port(
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rst : in std_logic;
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wclk : in std_logic;
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rclk : in std_logic;
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ReUse : in std_logic_vector(FifoCnt-1 downto 0);
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wen : in std_logic_vector(FifoCnt-1 downto 0);
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ren : in std_logic_vector(FifoCnt-1 downto 0);
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wdata : in std_logic_vector((FifoCnt*Data_sz)-1 downto 0);
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rdata : out std_logic_vector((FifoCnt*Data_sz)-1 downto 0);
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full : out std_logic_vector(FifoCnt-1 downto 0);
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empty : out std_logic_vector(FifoCnt-1 downto 0)
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);
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end component;
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component ssram_plugin is
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generic (tech : integer := 0);
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port
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(
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clk : in std_logic;
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mem_ctrlr_o : in memory_out_type;
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SSRAM_CLK : out std_logic;
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nBWa : out std_logic;
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nBWb : out std_logic;
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nBWc : out std_logic;
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nBWd : out std_logic;
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nBWE : out std_logic;
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nADSC : out std_logic;
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nADSP : out std_logic;
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nADV : out std_logic;
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nGW : out std_logic;
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nCE1 : out std_logic;
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CE2 : out std_logic;
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nCE3 : out std_logic;
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nOE : out std_logic;
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MODE : out std_logic;
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ZZ : out std_logic
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);
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end component;
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end;
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