##// END OF EJS Templates
Update SOLO_LFR_LFR-EM timings constraints...
Update SOLO_LFR_LFR-EM timings constraints (due to the fact that we used a A3PE3000L FPGA on the LFR-EM board)

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r217:13429b36c676 alexis
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vhdlsyn.txt
2 lines | 24 B | text/plain | TextLexer
DEMUX.vhd
lpp_demux.vhd