##// END OF EJS Templates
Update SOLO_LFR_LFR-EM timings constraints...
Update SOLO_LFR_LFR-EM timings constraints (due to the fact that we used a A3PE3000L FPGA on the LFR-EM board)

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vhdlsyn.txt
7 lines | 124 B | text/plain | TextLexer
lpp_cna.vhd
APB_LFR_CAL.vhd
RAM_READER.vhd
RAM_WRITER.vhd
SPI_DAC_DRIVER.vhd
dynamic_freq_div.vhd
lfr_cal_driver.vhd