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Update SOLO_LFR_LFR-EM timings constraints...
Update SOLO_LFR_LFR-EM timings constraints (due to the fact that we used a A3PE3000L FPGA on the LFR-EM board)
pellion - - Load All Authors

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r499:ac8423f90316 JC
r674:b0efa9138022 default
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vhdlsyn.txt
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/ lib / lpp / lpp_ad_Conv / vhdlsyn.txt
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lpp_ad_Conv.vhd
RHF1401.vhd
top_ad_conv_RHF1401.vhd
top_ad_conv_RHF1401_withFilter.vhd
TestModule_RHF1401.vhd
top_ad_conv_ADS7886_v2.vhd
ADS7886_drvr_v2.vhd
lpp_lfr_hk.vhd