##// END OF EJS Templates
Update SOLO_LFR_LFR-EM timings constraints...
Update SOLO_LFR_LFR-EM timings constraints (due to the fact that we used a A3PE3000L FPGA on the LFR-EM board)

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r191:cfe9287a48ea JC
r674:b0efa9138022 default
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top_ad_conv.vhd
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