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Update SOLO_LFR_LFR-EM timings constraints...
Update SOLO_LFR_LFR-EM timings constraints (due to the fact that we used a A3PE3000L FPGA on the LFR-EM board)
pellion - - Load All Authors

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r611:ec07182522e1 simu_with_Leon3
r674:b0efa9138022 default
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vhdlsyn.txt
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/ lib / lpp / lfr_management / vhdlsyn.txt
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lpp_lfr_management.vhd
lpp_lfr_management_apbreg_pkg.vhd
apb_lfr_management.vhd
apb_lfr_management_nocal.vhd
lfr_time_management.vhd
fine_time_counter.vhd
coarse_time_counter.vhd
fine_time_max_value_gen.vhd