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Update SOLO_LFR_LFR-EM timings constraints...
Update SOLO_LFR_LFR-EM timings constraints (due to the fact that we used a A3PE3000L FPGA on the LFR-EM board)
pellion - - Load All Authors

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r657:448d3f8e2d47 default
r674:b0efa9138022 default
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vhdlsyn.txt
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/ lib / lpp / general_purpose / vhdlsyn.txt
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data_type_pkg.vhd
general_purpose.vhd
ADDRcntr.vhd
ALU.vhd
Adder.vhd
Clk_Divider2.vhd
Clk_divider.vhd
MAC.vhd
MAC_CONTROLER.vhd
MAC_MUX.vhd
MAC_MUX2.vhd
MAC_REG.vhd
MUX2.vhd
MUXN.vhd
Multiplier.vhd
REG.vhd
SYNC_FF.vhd
Shifter.vhd
TwoComplementer.vhd
Clock_Divider.vhd
lpp_front_to_level.vhd
lpp_front_detection.vhd
lpp_front_positive_detection.vhd
SYNC_VALID_BIT.vhd
RR_Arbiter_4.vhd
general_counter.vhd
ramp_generator.vhd
TimeGenAdvancedTrigger.vhd
saturation.vhd