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------------------------------------------------------------------------------
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-- This file is a part of the LPP VHDL IP LIBRARY
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-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-------------------------------------------------------------------------------
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-- Author : Alexis Jeandet
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-- Mail : alexis.jeandet@lpp.polytechnique.fr
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----------------------------------------------------------------------------
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--UPDATE
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-------------------------------------------------------------------------------
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-- 14-03-2013 - Jean-christophe Pellion
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-- ADD MUXN (a parametric multiplexor (N stage of MUX2))
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-------------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE IEEE.NUMERIC_STD.ALL;
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PACKAGE general_purpose IS
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COMPONENT saturation
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generic (
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SIZE_INPUT : integer := 18;
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SIZE_OUTPUT : integer := 16);
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port (
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s_in : in std_logic_vector(SIZE_INPUT-1 downto 0);
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s_out : out std_logic_vector(SIZE_OUTPUT-1 downto 0) );
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end COMPONENT;
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COMPONENT general_counter
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GENERIC (
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CYCLIC : STD_LOGIC := '1';
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NB_BITS_COUNTER : INTEGER := 9;
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RST_VALUE : INTEGER := 0);
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PORT (
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clk : IN STD_LOGIC;
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rstn : IN STD_LOGIC;
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MAX_VALUE : IN STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0) := (OTHERS => '1');
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set : IN STD_LOGIC;
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set_value : IN STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0);
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add1 : IN STD_LOGIC;
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counter : OUT STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0));
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END COMPONENT;
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COMPONENT Clk_divider IS
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GENERIC(OSC_freqHz : INTEGER := 50000000;
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TargetFreq_Hz : INTEGER := 50000);
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PORT (clk : IN STD_LOGIC;
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reset : IN STD_LOGIC;
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clk_divided : OUT STD_LOGIC);
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END COMPONENT;
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COMPONENT Clk_divider2 IS
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GENERIC(N : INTEGER := 16);
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PORT(
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clk_in : IN STD_LOGIC;
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clk_out : OUT STD_LOGIC);
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END COMPONENT;
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COMPONENT Adder IS
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GENERIC(
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Input_SZ_A : INTEGER := 16;
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Input_SZ_B : INTEGER := 16
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);
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PORT(
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clk : IN STD_LOGIC;
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reset : IN STD_LOGIC;
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clr : IN STD_LOGIC;
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load : IN STD_LOGIC;
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add : IN STD_LOGIC;
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OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
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OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
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RES : OUT STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0)
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);
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END COMPONENT;
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COMPONENT Adder_V0 IS
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GENERIC(
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Input_SZ_A : INTEGER := 16;
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Input_SZ_B : INTEGER := 16
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);
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PORT(
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clk : IN STD_LOGIC;
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reset : IN STD_LOGIC;
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clr : IN STD_LOGIC;
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add : IN STD_LOGIC;
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OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
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OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
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RES : OUT STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0)
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);
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END COMPONENT;
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COMPONENT ADDRcntr IS
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PORT(
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clk : IN STD_LOGIC;
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reset : IN STD_LOGIC;
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count : IN STD_LOGIC;
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clr : IN STD_LOGIC;
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Q : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
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);
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END COMPONENT;
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COMPONENT ALU IS
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GENERIC(
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Arith_en : INTEGER := 1;
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Logic_en : INTEGER := 1;
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Input_SZ_1 : INTEGER := 16;
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Input_SZ_2 : INTEGER := 9;
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COMP_EN : INTEGER := 0 -- 1 => No Comp
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);
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PORT(
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clk : IN STD_LOGIC;
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reset : IN STD_LOGIC;
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ctrl : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
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comp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
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OP1 : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0);
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OP2 : IN STD_LOGIC_VECTOR(Input_SZ_2-1 DOWNTO 0);
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RES : OUT STD_LOGIC_VECTOR(Input_SZ_1+Input_SZ_2-1 DOWNTO 0)
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);
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END COMPONENT;
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COMPONENT ALU_V0 IS
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GENERIC(
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Arith_en : INTEGER := 1;
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Logic_en : INTEGER := 1;
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Input_SZ_1 : INTEGER := 16;
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Input_SZ_2 : INTEGER := 9
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);
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PORT(
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clk : IN STD_LOGIC;
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reset : IN STD_LOGIC;
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ctrl : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
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OP1 : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0);
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OP2 : IN STD_LOGIC_VECTOR(Input_SZ_2-1 DOWNTO 0);
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RES : OUT STD_LOGIC_VECTOR(Input_SZ_1+Input_SZ_2-1 DOWNTO 0)
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);
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END COMPONENT;
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COMPONENT MAC_V0 IS
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GENERIC(
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Input_SZ_A : INTEGER := 8;
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Input_SZ_B : INTEGER := 8
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);
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PORT(
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clk : IN STD_LOGIC;
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reset : IN STD_LOGIC;
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clr_MAC : IN STD_LOGIC;
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MAC_MUL_ADD : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
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OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
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OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
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RES : OUT STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0)
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);
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END COMPONENT;
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---------------------------------------------------------
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-------- // Sélection grace a l'entrée "ctrl" \\ --------
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---------------------------------------------------------
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CONSTANT ctrl_IDLE : STD_LOGIC_VECTOR(2 DOWNTO 0) := "000";
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CONSTANT ctrl_MAC : STD_LOGIC_VECTOR(2 DOWNTO 0) := "001";
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CONSTANT ctrl_MULT : STD_LOGIC_VECTOR(2 DOWNTO 0) := "010";
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CONSTANT ctrl_ADD : STD_LOGIC_VECTOR(2 DOWNTO 0) := "011";
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CONSTANT ctrl_CLRMAC : STD_LOGIC_VECTOR(2 DOWNTO 0) := "100";
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CONSTANT IDLE_V0 : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0000";
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CONSTANT MAC_op_V0 : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0001";
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CONSTANT MULT_V0 : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0010";
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CONSTANT ADD_V0 : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0011";
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CONSTANT CLR_MAC_V0 : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0100";
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---------------------------------------------------------
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COMPONENT MAC IS
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GENERIC(
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Input_SZ_A : INTEGER := 8;
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Input_SZ_B : INTEGER := 8;
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COMP_EN : INTEGER := 0 -- 1 => No Comp
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);
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PORT(
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clk : IN STD_LOGIC;
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reset : IN STD_LOGIC;
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clr_MAC : IN STD_LOGIC;
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MAC_MUL_ADD : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
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Comp_2C : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
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OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
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OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
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RES : OUT STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0)
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);
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END COMPONENT;
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COMPONENT TwoComplementer IS
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GENERIC(
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Input_SZ : INTEGER := 16);
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PORT(
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clk : IN STD_LOGIC; --! Horloge du composant
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reset : IN STD_LOGIC; --! Reset general du composant
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clr : IN STD_LOGIC; --! Un reset spécifique au programme
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TwoComp : IN STD_LOGIC; --! Autorise l'utilisation du complément
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OP : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0); --! Opérande d'entrée
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RES : OUT STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0) --! Résultat, opérande complémenté ou non
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);
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END COMPONENT;
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COMPONENT MAC_CONTROLER IS
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PORT(
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ctrl : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
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MULT : OUT STD_LOGIC;
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ADD : OUT STD_LOGIC;
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-- LOAD_ADDER : out std_logic;
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MACMUX_sel : OUT STD_LOGIC;
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MACMUX2_sel : OUT STD_LOGIC
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);
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END COMPONENT;
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COMPONENT MAC_MUX IS
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GENERIC(
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Input_SZ_A : INTEGER := 16;
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Input_SZ_B : INTEGER := 16
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);
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PORT(
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sel : IN STD_LOGIC;
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INA1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
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INA2 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
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INB1 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
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INB2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
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OUTA : OUT STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
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OUTB : OUT STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0)
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);
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END COMPONENT;
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COMPONENT MAC_MUX2 IS
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GENERIC(Input_SZ : INTEGER := 16);
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PORT(
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sel : IN STD_LOGIC;
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RES1 : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
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RES2 : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
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RES : OUT STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0)
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);
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END COMPONENT;
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COMPONENT MAC_REG IS
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GENERIC(size : INTEGER := 16);
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PORT(
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reset : IN STD_LOGIC;
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clk : IN STD_LOGIC;
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D : IN STD_LOGIC_VECTOR(size-1 DOWNTO 0);
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Q : OUT STD_LOGIC_VECTOR(size-1 DOWNTO 0)
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);
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END COMPONENT;
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COMPONENT MUX2 IS
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GENERIC(Input_SZ : INTEGER := 16);
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PORT(
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sel : IN STD_LOGIC;
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IN1 : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
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IN2 : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
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RES : OUT STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0)
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);
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END COMPONENT;
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TYPE MUX_INPUT_TYPE IS ARRAY (NATURAL RANGE <>, NATURAL RANGE <>) OF STD_LOGIC;
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TYPE MUX_OUTPUT_TYPE IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC;
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COMPONENT MUXN
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GENERIC (
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Input_SZ : INTEGER;
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NbStage : INTEGER);
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PORT (
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sel : IN STD_LOGIC_VECTOR(NbStage-1 DOWNTO 0);
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INPUT : IN MUX_INPUT_TYPE(0 TO (2**NbStage)-1, Input_SZ-1 DOWNTO 0);
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--INPUT : IN ARRAY (0 TO (2**NbStage)-1) OF STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
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RES : OUT MUX_OUTPUT_TYPE(Input_SZ-1 DOWNTO 0));
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END COMPONENT;
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COMPONENT Multiplier IS
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GENERIC(
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Input_SZ_A : INTEGER := 16;
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Input_SZ_B : INTEGER := 16
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);
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PORT(
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clk : IN STD_LOGIC;
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reset : IN STD_LOGIC;
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mult : IN STD_LOGIC;
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OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
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OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
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RES : OUT STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0)
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);
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END COMPONENT;
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COMPONENT REG IS
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GENERIC(size : INTEGER := 16; initial_VALUE : INTEGER := 0);
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PORT(
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reset : IN STD_LOGIC;
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clk : IN STD_LOGIC;
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D : IN STD_LOGIC_VECTOR(size-1 DOWNTO 0);
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Q : OUT STD_LOGIC_VECTOR(size-1 DOWNTO 0)
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);
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END COMPONENT;
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COMPONENT RShifter IS
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|
GENERIC(
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|
Input_SZ : INTEGER := 16;
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|
shift_SZ : INTEGER := 4
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);
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PORT(
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|
clk : IN STD_LOGIC;
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|
reset : IN STD_LOGIC;
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|
shift : IN STD_LOGIC;
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OP : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
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|
cnt : IN STD_LOGIC_VECTOR(shift_SZ-1 DOWNTO 0);
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RES : OUT STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0)
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);
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END COMPONENT;
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COMPONENT SYNC_FF
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|
|
GENERIC (
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|
|
NB_FF_OF_SYNC : INTEGER);
|
|
|
PORT (
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|
|
clk : IN STD_LOGIC;
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|
rstn : IN STD_LOGIC;
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|
A : IN STD_LOGIC;
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|
A_sync : OUT STD_LOGIC);
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|
|
END COMPONENT;
|
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|
|
|
COMPONENT lpp_front_to_level
|
|
|
PORT (
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|
|
clk : IN STD_LOGIC;
|
|
|
rstn : IN STD_LOGIC;
|
|
|
sin : IN STD_LOGIC;
|
|
|
sout : OUT STD_LOGIC);
|
|
|
END COMPONENT;
|
|
|
|
|
|
COMPONENT lpp_front_detection
|
|
|
PORT (
|
|
|
clk : IN STD_LOGIC;
|
|
|
rstn : IN STD_LOGIC;
|
|
|
sin : IN STD_LOGIC;
|
|
|
sout : OUT STD_LOGIC);
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|
|
END COMPONENT;
|
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|
|
COMPONENT lpp_front_positive_detection
|
|
|
PORT (
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|
|
clk : IN STD_LOGIC;
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|
rstn : IN STD_LOGIC;
|
|
|
sin : IN STD_LOGIC;
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|
|
sout : OUT STD_LOGIC);
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|
END COMPONENT;
|
|
|
|
|
|
--COMPONENT SYNC_VALID_BIT
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|
|
-- GENERIC (
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|
|
-- NB_FF_OF_SYNC : INTEGER);
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|
|
-- PORT (
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|
|
-- clk_in : IN STD_LOGIC;
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|
|
-- clk_out : IN STD_LOGIC;
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|
|
-- rstn : IN STD_LOGIC;
|
|
|
-- sin : IN STD_LOGIC;
|
|
|
-- sout : OUT STD_LOGIC);
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|
|
--END COMPONENT;
|
|
|
|
|
|
COMPONENT SYNC_VALID_BIT
|
|
|
GENERIC (
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|
|
NB_FF_OF_SYNC : INTEGER);
|
|
|
PORT (
|
|
|
clk_in : IN STD_LOGIC;
|
|
|
rstn_in : IN STD_LOGIC;
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|
|
clk_out : IN STD_LOGIC;
|
|
|
rstn_out : IN STD_LOGIC;
|
|
|
sin : IN STD_LOGIC;
|
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|
sout : OUT STD_LOGIC);
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END COMPONENT;
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COMPONENT RR_Arbiter_4
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|
PORT (
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clk : IN STD_LOGIC;
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|
rstn : IN STD_LOGIC;
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|
in_valid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
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out_grant : OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
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|
END COMPONENT;
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|
|
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|
COMPONENT Clock_Divider IS
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GENERIC(N : INTEGER := 10);
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|
PORT(
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|
clk, rst : IN STD_LOGIC;
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|
|
sclk : OUT STD_LOGIC);
|
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|
END COMPONENT;
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|
|
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|
COMPONENT ramp_generator
|
|
|
GENERIC (
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|
|
DATA_SIZE : INTEGER;
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|
|
VALUE_UNSIGNED_INIT : INTEGER;
|
|
|
VALUE_UNSIGNED_INCR : INTEGER;
|
|
|
VALUE_UNSIGNED_MASK : INTEGER);
|
|
|
PORT (
|
|
|
clk : IN STD_LOGIC;
|
|
|
rstn : IN STD_LOGIC;
|
|
|
new_data : IN STD_LOGIC;
|
|
|
output_data : OUT STD_LOGIC_VECTOR(DATA_SIZE-1 DOWNTO 0));
|
|
|
END COMPONENT;
|
|
|
|
|
|
COMPONENT TimeGenAdvancedTrigger
|
|
|
PORT(
|
|
|
clk : IN STD_LOGIC;
|
|
|
rstn : IN STD_LOGIC;
|
|
|
|
|
|
SPW_Tickout : IN STD_LOGIC;
|
|
|
|
|
|
CoarseTime : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
|
|
FineTime : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
|
|
|
|
|
|
TrigPeriod : IN STD_LOGIC_VECTOR(3 DOWNTO 0); -- In seconds 0 to 15
|
|
|
TrigShift : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- In FineTime steps
|
|
|
Restart : IN STD_LOGIC;
|
|
|
StartDate : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- Date in seconds since epoch
|
|
|
|
|
|
BypassTickout : IN STD_LOGIC; -- if set then Trigger output is driven by SPW tickout
|
|
|
-- else Trigger output is driven by advanced trig
|
|
|
Trigger : OUT STD_LOGIC
|
|
|
|
|
|
);
|
|
|
END COMPONENT;
|
|
|
|
|
|
END;
|
|
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|