##// END OF EJS Templates
Update SOLO_LFR_LFR-EM timings constraints...
Update SOLO_LFR_LFR-EM timings constraints (due to the fact that we used a A3PE3000L FPGA on the LFR-EM board)

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r604:9d0c406efed4 simu_with_Leon3
r674:b0efa9138022 default
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vhdlsyn.txt
4 lines | 73 B | text/plain | TextLexer
window_function_pkg.vhd
window_function.vhd
WF_processing.vhd
WF_rom.vhd