HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib Files · designs/Validation_CIC_LFR/run_add_sub.do

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HG_REPOSITORIES » LPP » INSTRUMENTATION » USERS » PELLION » VHD_Lib

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Clone from http://pc-instru.lpp.polytechnique.fr:5000/VHD_Lib

Update SOLO_LFR_LFR-EM timings constraints...

Update SOLO_LFR_LFR-EM timings constraints (due to the fact that we used a A3PE3000L FPGA on the LFR-EM board)

pellion - - Load All Authors

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r500:50f24bdc968c JC


                r674:b0efa9138022

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             run_add_sub.do
        
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      vcom -quiet  -93  -work lpp  ../../lib/lpp/dsp/cic/cic_pkg.vhd

      vcom -quiet  -93  -work lpp  ../../lib/lpp/dsp/cic/cic_lfr_add_sub.vhd

      vcom -quiet  -93  -work work tb_cic_lfr_add_sub.vhd

      vsim work.testbench

      log -r *

      do wave_add_sub.do

      run -all

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				vcom -quiet -93 -work lpp ../../lib/lpp/dsp/cic/cic_pkg.vhd
				vcom -quiet -93 -work lpp ../../lib/lpp/dsp/cic/cic_lfr_add_sub.vhd

				vcom -quiet -93 -work work tb_cic_lfr_add_sub.vhd

				vsim work.testbench

				log -r *

				do wave_add_sub.do

				run -all