HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib Files · designs/ICI4-3DCAM-Integ1/systest.c

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HG_REPOSITORIES » LPP » INSTRUMENTATION » USERS » PELLION » VHD_Lib

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Clone from http://pc-instru.lpp.polytechnique.fr:5000/VHD_Lib

Update SOLO_LFR_LFR-EM timings constraints...

Update SOLO_LFR_LFR-EM timings constraints (due to the fact that we used a A3PE3000L FPGA on the LFR-EM board)

pellion - - Load All Authors

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r639:5ffe6bd0368c default


                r674:b0efa9138022

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             systest.c
        
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      main()

      {

      	report_start();

      //	svgactrl_test(0x80000600, 1, 0, 0x40200000, -1, 0, 0);

      	base_test();

      /*

              greth_test(0x80000e00);

      	spw_test(0x80100A00);

      	spw_test(0x80100B00);

      	spw_test(0x80100C00);

      	svgactrl_test(0x80000600, 1, 0, 0x40200000, -1, 0, 0);

      */

              report_end();

      }

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				main()

				{
				report_start();


				// svgactrl_test(0x80000600, 1, 0, 0x40200000, -1, 0, 0);
				base_test();
				/*
				greth_test(0x80000e00);
				spw_test(0x80100A00);
				spw_test(0x80100B00);
				spw_test(0x80100C00);
				svgactrl_test(0x80000600, 1, 0, 0x40200000, -1, 0, 0);
				*/
				report_end();
				}