##// END OF EJS Templates
HG_REPOSITORIES » LPP » INSTRUMENTATION » USERS » PELLION » VHD_Lib
RSS

Clone from http://pc-instru.lpp.polytechnique.fr:5000/VHD_Lib

Update SOLO_LFR_LFR-EM timings constraints...
Update SOLO_LFR_LFR-EM timings constraints (due to the fact that we used a A3PE3000L FPGA on the LFR-EM board)
jeandet - - Load All Authors

File last commit:

r168:0b190be76d60 alexis
r674:b0efa9138022 default
Show More
ici4.ut
32 lines | 507 B | text/plain | TextLexer
/ designs / ICI4-3DCAM-Integ1 / ici4.ut
History | Annotation | Raw |Copy content |Copy permalink
-w
-g DebugBitstream:No
-d
-g Binary:no
-g CRC:Enable
-g Reset_on_err:No
-g ConfigRate:25
-g ProgPin:PullUp
-g DonePin:PullUp
-g TckPin:PullUp
-g TdiPin:PullUp
-g TdoPin:PullUp
-g TmsPin:PullUp
-g UnusedPin:PullDown
-g UserID:0xFFFFFFFF
-g StartUpClk:CClk
-g DONE_cycle:4
-g GTS_cycle:5
-g GWE_cycle:6
-g LCK_cycle:NoWait
-g Security:None
-g Persist:No
-m
-g ReadBack
-g DonePipe:Yes
-g DriveDone:Yes
-g en_sw_gsr:No
-g en_porb:Yes
-g drive_awake:No
-g sw_clk:Startupclk
-g sw_gwe_cycle:5
-g sw_gts_cycle:4