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LIBRARY IEEE;
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USE IEEE.STD_LOGIC_1164.ALL;
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USE IEEE.NUMERIC_STD.ALL;
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ENTITY fine_time_max_value_gen IS
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PORT (
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clk : IN STD_LOGIC;
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rstn : IN STD_LOGIC;
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tick : IN STD_LOGIC;
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fine_time_add : IN STD_LOGIC;
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fine_time_max_value : OUT STD_LOGIC_VECTOR(8 DOWNTO 0)
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);
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END fine_time_max_value_gen;
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ARCHITECTURE beh OF fine_time_max_value_gen IS
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SIGNAL count_even : STD_LOGIC;
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SIGNAL count_first : STD_LOGIC;
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SIGNAL count_modulo_33 : STD_LOGIC;
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SIGNAL count_33 : INTEGER range 0 TO 32;
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BEGIN -- beh
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fine_time_max_value <= STD_LOGIC_VECTOR(to_unsigned(381,9)) WHEN count_first = '1' ELSE
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STD_LOGIC_VECTOR(to_unsigned(380,9)) WHEN count_even = count_modulo_33 ELSE
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STD_LOGIC_VECTOR(to_unsigned(381,9)) WHEN count_even = '1' ELSE
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STD_LOGIC_VECTOR(to_unsigned(379,9)) WHEN count_modulo_33 = '1' ELSE
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STD_LOGIC_VECTOR(to_unsigned(380,9));
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PROCESS (clk, rstn)
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BEGIN -- PROCESS
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IF rstn = '0' THEN -- asynchronous reset (active low)
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count_first <= '1';
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count_even <= '0';
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count_modulo_33 <= '0';
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count_33 <= 0;
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ELSIF clk'event AND clk = '1' THEN -- rising clock edge
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IF tick = '1' THEN
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count_even <= '0';
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count_first <= '1';
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count_modulo_33 <= '0';
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count_33 <= 0;
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ELSE
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IF fine_time_add = '1' THEN
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count_first <= '0';
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IF count_even = '1' THEN
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count_even <= '0';
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ELSE
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count_even <= '1';
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END IF;
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IF count_33 = 31 THEN
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count_modulo_33 <= '1';
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ELSE
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count_modulo_33 <= '0';
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END IF;
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IF count_33 = 32 THEN
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count_33 <= 0;
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ELSE
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count_33 <= count_33 + 1;
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END IF;
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END IF;
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END IF;
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END IF;
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END PROCESS;
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END beh;
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