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------------------------------------------------------------------------------
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-- This file is a part of the LPP VHDL IP LIBRARY
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-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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------------------------------------------------------------------------------
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-- Author : Martin Morlot
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-- Mail : martin.morlot@lpp.polytechnique.fr
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------------------------------------------------------------------------------
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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library LPP;
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use lpp.lpp_cna.all;
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--! Programme du Convertisseur Numrique/Analogique
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entity DacDriver is
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generic(cpt_serial : integer := 6); --! Gnrique contenant le rsultat de la division clk/sclk !!! clk=25Mhz
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port(
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clk : in std_logic; --! Horloge du composant
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rst : in std_logic; --! Reset general du composant
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enable : in std_logic; --! Autorise ou non l'utilisation du composant
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Data_IN : in std_logic_vector(15 downto 0); --! Donne Numrique d'entre sur 16 bits
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SYNC : out std_logic; --! Signal de synchronisation du convertisseur
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SCLK : out std_logic; --! Horloge systeme du convertisseur
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Readn : out std_logic;
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Ready : out std_logic; --! Flag, signale la fin de la srialisation d'une donne
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Data : out std_logic --! Donne numrique srialis
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);
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end entity;
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--! @details Un driver C va permettre de gnerer un tableau de donnes sur 16 bits,
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--! qui seront srialis pour tre ensuite diriges vers le convertisseur.
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architecture ar_DacDriver of DacDriver is
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signal s_SCLK : std_logic;
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signal Send : std_logic;
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begin
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SystemCLK : Systeme_Clock
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generic map (cpt_serial)
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port map (clk,rst,s_SCLK);
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Signal_sync : Gene_SYNC
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port map (s_SCLK,rst,enable,Send,SYNC);
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Serial : serialize
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port map (clk,rst,s_SCLK,Data_IN,Send,Ready,Data);
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RenGEN : ReadFifo_GEN
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port map (clk,rst,Send,Readn);
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SCLK <= s_SCLK;
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end architecture;
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