HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib Files · designs/ProjetBlanc-LeonLPP-M7A3P1k/synthesis/leon3mp_sdc.sdc

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HG_REPOSITORIES » LPP » INSTRUMENTATION » USERS » PELLION » VHD_Lib

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/ designs / ProjetBlanc-LeonLPP-M7A3P1k / synthesis / leon3mp_sdc.sdc

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				# Top Level Design Parameters

				# Clocks

				create_clock -period 10.000000 -waveform {0.000000 5.000000} clk50MHz

				# False Paths Between Clocks


				# False Path Constraints


				# Maximum Delay Constraints


				# Multicycle Constraints


				# Virtual Clocks
				# Output Load Constraints
				# Driving Cell Constraints
				# Wire Loads
				# set_wire_load_mode top

				# Other Constraints

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