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------------------------------------------------------------------------------
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-- This file is a part of the LPP VHDL IP LIBRARY
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-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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------------------------------------------------------------------------------
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-- Author : Martin Morlot
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-- Mail : martin.morlot@lpp.polytechnique.fr
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------------------------------------------------------------------------------
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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use work.FFT_config.all;
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entity Flag_Extremum is
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port(
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clk,raz : in std_logic;
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load : in std_logic;
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y_rdy : in std_logic;
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d_valid_WR : in std_logic;
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read_y_RE : in std_logic;
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full : out std_logic;
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empty : out std_logic
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);
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end Flag_Extremum;
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architecture ar_Flag_Extremum of Flag_Extremum is
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type etat is (eA,eB,eC,eD,eX,e0,e1,e2,e3);
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signal ect : etat;
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signal load_reg : std_logic;
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signal y_rdy_reg : std_logic;
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signal RE_reg : std_logic;
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signal WR_reg : std_logic;
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begin
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process (clk,raz)
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begin
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if(raz='0')then
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full <= '0';
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empty <= '1';
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ect <= eA;
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elsif(clk' event and clk='1')then
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load_reg <= load;
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y_rdy_reg <= y_rdy;
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RE_reg <= read_y_RE;
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WR_reg <= d_valid_WR;
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case ect is
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when eA =>
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if(WR_reg='0' and d_valid_WR='1')then
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empty <= '0';
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ect <= eB;
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end if;
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when eB =>
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if(load_reg='1' and load='0')then
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ect <= eC;
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end if;
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when eC =>
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if(load_reg='1' and load='0')then
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full <= '1';
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ect <= eD;
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end if;
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when eD =>
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if(RE_reg='0' and read_y_RE='1')then
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full <= '0';
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ect <= eX;
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end if;
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when eX =>
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empty <= '1';
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ect <= e0;
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when e0 =>
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if(WR_reg='0' and d_valid_WR='1')then
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empty <= '0';
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ect <= e1;
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end if;
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when e1 =>
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if(load_reg='1' and load='0')then
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full <= '1';
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ect <= e2;
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end if;
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when e2 =>
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if(RE_reg='0' and read_y_RE='1')then
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full <= '0';
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ect <= e3;
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end if;
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when e3 =>
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if(y_rdy_reg='1' and y_rdy='0')then
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empty <= '1';
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ect <= e0;
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end if;
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end case;
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end if;
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end process;
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end ar_Flag_Extremum;
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