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------------------------------------------------------------------------------
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-- This file is a part of the LPP VHDL IP LIBRARY
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-- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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------------------------------------------------------------------------------
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-- Author : Martin Morlot
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-- Mail : martin.morlot@lpp.polytechnique.fr
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------------------------------------------------------------------------------
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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library lpp;
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use lpp.lpp_memory.all;
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library techmap;
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use techmap.gencomp.all;
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entity lppFIFOxN is
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generic(
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tech : integer := 0;
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Data_sz : integer range 1 to 32 := 8;
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Addr_sz : integer range 1 to 32 := 8;
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FifoCnt : integer := 1;
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Enable_ReUse : std_logic := '0'
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);
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port(
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rst : in std_logic;
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wclk : in std_logic;
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rclk : in std_logic;
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ReUse : in std_logic_vector(FifoCnt-1 downto 0);
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wen : in std_logic_vector(FifoCnt-1 downto 0);
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ren : in std_logic_vector(FifoCnt-1 downto 0);
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wdata : in std_logic_vector((FifoCnt*Data_sz)-1 downto 0);
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rdata : out std_logic_vector((FifoCnt*Data_sz)-1 downto 0);
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full : out std_logic_vector(FifoCnt-1 downto 0);
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empty : out std_logic_vector(FifoCnt-1 downto 0)
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);
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end entity;
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architecture ar_lppFIFOxN of lppFIFOxN is
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begin
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fifos: for i in 0 to FifoCnt-1 generate
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FIFO0 : lpp_fifo
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generic map (tech,Enable_ReUse,Data_sz,Addr_sz)
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port map(rst,ReUse(i),rclk,ren(i),rdata((i+1)*Data_sz-1 downto i*Data_sz),empty(i),open,wclk,wen(i),wdata((i+1)*Data_sz-1 downto i*Data_sz),full(i),open);
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end generate;
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end architecture;
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