HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib Files · lib/lpp/lpp_waveform/vhdlsyn.txt

temp : update ADC driver...

temp : update ADC driver - conversion part clocked by clk_49 (49.152 MHz) - cnv_clk = clk_49.152/100 with duty cycle of 50% - 3 period for each Ren, - Data sampling during the 2nd cycle of Ren, - each 2 data input, 1 data output (@)

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simu_with_Leon3

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/ lib / lpp / lpp_waveform / vhdlsyn.txt

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				lpp_waveform_pkg.vhd
				lpp_waveform.vhd
				lpp_waveform_burst.vhd
				lpp_waveform_fifo_withoutLatency.vhd
				lpp_waveform_fifo_latencyCorrection.vhd
				lpp_waveform_fifo.vhd
				lpp_waveform_fifo_arbiter.vhd
				lpp_waveform_fifo_ctrl.vhd
				lpp_waveform_fifo_headreg.vhd
				lpp_waveform_snapshot.vhd
				lpp_waveform_snapshot_controler.vhd
				lpp_waveform_genaddress.vhd
				lpp_waveform_dma_genvalid.vhd
				lpp_waveform_fifo_arbiter_reg.vhd
				lpp_waveform_fsmdma.vhd

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