##// END OF EJS Templates
HG_REPOSITORIES » LPP » INSTRUMENTATION » USERS » PELLION » VHD_Lib
RSS

Clone from http://pc-instru.lpp.polytechnique.fr:5000/VHD_Lib

temp : update ADC driver...
temp : update ADC driver - conversion part clocked by clk_49 (49.152 MHz) - cnv_clk = clk_49.152/100 with duty cycle of 50% - 3 period for each Ren, - Data sampling during the 2nd cycle of Ren, - each 2 data input, 1 data output (@)
pellion - - Load All Authors

File last commit:

r588:86f47bdf2a6e simu_with_Leon3
r594:a9702b7364d2 simu_with_Leon3
Show More
vhdlsyn.txt
27 lines | 423 B | text/plain | TextLexer
/ lib / lpp / general_purpose / vhdlsyn.txt
History | Annotation | Raw |Copy content |Copy permalink
data_type_pkg.vhd
general_purpose.vhd
ADDRcntr.vhd
ALU.vhd
Adder.vhd
Clk_Divider2.vhd
Clk_divider.vhd
MAC.vhd
MAC_CONTROLER.vhd
MAC_MUX.vhd
MAC_MUX2.vhd
MAC_REG.vhd
MUX2.vhd
MUXN.vhd
Multiplier.vhd
REG.vhd
SYNC_FF.vhd
Shifter.vhd
TwoComplementer.vhd
Clock_Divider.vhd
lpp_front_to_level.vhd
lpp_front_detection.vhd
lpp_front_positive_detection.vhd
SYNC_VALID_BIT.vhd
RR_Arbiter_4.vhd
general_counter.vhd
ramp_generator.vhd