HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib Files · lib/lpp/general_purpose/Clk_Divider2.vhd

temp : update ADC driver...

temp : update ADC driver - conversion part clocked by clk_49 (49.152 MHz) - cnv_clk = clk_49.152/100 with duty cycle of 50% - 3 period for each Ren, - Data sampling during the 2nd cycle of Ren, - each 2 data input, 1 data output (@)

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             Clk_Divider2.vhd
        
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      -- ClkDivider.vhd

      library IEEE;

      use IEEE.std_logic_1164.all;

      use IEEE.numeric_std.all;

      entity Clk_Divider2 is 

      generic(N : integer := 16);

      port(

          clk_in  :   in  std_logic;

          clk_out :   out std_logic

      );

      end entity;

      architecture ar_ClkDivider of Clk_Divider2 is

      signal  cpt     :   integer range 0 to N/2-1;

      signal  clk_int :   std_logic:='0';

      begin

      clk_out <=  clk_int;

      process(clk_in)

      begin

          if clk_in'event and clk_in = '1' then

              if cpt = N/2-1 then

                  clk_int <= not clk_int;

                  cpt       <=  0;

              else

                  cpt       <=  cpt + 1;

              end if;

          end if;

      end process;

      end ar_ClkDivider;

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				-- ClkDivider.vhd
				library IEEE;
				use IEEE.std_logic_1164.all;
				use IEEE.numeric_std.all;



				entity Clk_Divider2 is
				generic(N : integer := 16);
				port(
				clk_in : in std_logic;
				clk_out : out std_logic
				);
				end entity;



				architecture ar_ClkDivider of Clk_Divider2 is
				signal cpt : integer range 0 to N/2-1;
				signal clk_int : std_logic:='0';
				begin

				clk_out <= clk_int;

				process(clk_in)
				begin
				if clk_in'event and clk_in = '1' then
				if cpt = N/2-1 then
				clk_int <= not clk_int;
				cpt <= 0;
				else
				cpt <= cpt + 1;
				end if;
				end if;
				end process;
				end ar_ClkDivider;